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PRODID:UW-Physics-TWaP
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UID:UW-Physics-Event-2962
DTSTART:20130305T100000
DURATION:PT1H0M0S
LOCATION:5280 Chamberlin Hall
SUMMARY:Analysis of high-fidelity gate design and error thresholds for fault-tolerant superconducting quantum computing architectures\, R. G. Herb Condensed Matter Seminar\, Joydip Ghosh\, University of Georgia
DESCRIPTION:Quantum computing with superconducting elements promises scalability and is widely regarded as a viable approach to develop a fault-tolerant architecture of a candidate quantum computer. In this talk\, I first discuss our recent proposal to design high-fidelity controlled-&#963;<sup>z</sup> (CZ) operations  using only DC bias control and then explore the performance of various existing superconducting surface code based architectures under a realistic multi-parameter error model. Assuming phase or transmon qubits and using only low frequency qubit-bias control\, our CZ operation exhibits threshold fidelity (intrinsic) with a realistic two-parameter pulse profile. In addition we have an analytic model that estimates the fidelities of CZ gates as a function of various pulse parameters as well as quantifies the error due to any perturbation over an optimal pulse shape. Next we consider a realistic\, multi-parameter error model and investigate the performance of the surface code for three possible fault-tolerant superconducting architectures. We map amplitude and phase damping to an asymmetric depolarization channel via the Pauli twirl approximation\, and obtain the logical error rate as a function of the qubit coherence time\, intrinsic state preparation and gate and readout errors. A numerical Monte Carlo simulation is performed to obtain the logical error rates and a leading order analytic model is constructed to estimate their scaling behavior below threshold. Our results suggest that large-scale fault-tolerant quantum computation should be possible with existing superconducting devices. 
URL:http://www.physics.wisc.edu/twap/view.php?id=2962
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