TimeQuest Timing Analyzer report for DE0_Nano
Wed Sep 25 10:23:22 2013
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
 15. Slow 1200mV 85C Model Setup: 'altera_reserved_tck'
 16. Slow 1200mV 85C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
 17. Slow 1200mV 85C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
 18. Slow 1200mV 85C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
 19. Slow 1200mV 85C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
 20. Slow 1200mV 85C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
 21. Slow 1200mV 85C Model Hold: 'CLOCK_50'
 22. Slow 1200mV 85C Model Hold: 'altera_reserved_tck'
 23. Slow 1200mV 85C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
 24. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
 25. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'
 26. Slow 1200mV 85C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
 27. Slow 1200mV 85C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
 28. Slow 1200mV 85C Model Removal: 'altera_reserved_tck'
 29. Slow 1200mV 85C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
 30. Slow 1200mV 85C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
 31. Slow 1200mV 85C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
 32. Slow 1200mV 85C Model Removal: 'CLOCK_50'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
 38. Setup Times
 39. Hold Times
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Output Enable Times
 43. Minimum Output Enable Times
 44. Output Disable Times
 45. Minimum Output Disable Times
 46. MTBF Summary
 47. Synchronizer Summary
 48. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years
 49. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years
 50. Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years
 51. Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years
 52. Synchronizer Chain #5: Typical MTBF is Greater than 1 Billion Years
 53. Synchronizer Chain #6: Typical MTBF is Greater than 1 Billion Years
 54. Synchronizer Chain #7: Typical MTBF is Greater than 1 Billion Years
 55. Synchronizer Chain #8: Typical MTBF is Greater than 1 Billion Years
 56. Synchronizer Chain #9: Typical MTBF is Greater than 1 Billion Years
 57. Synchronizer Chain #10: Typical MTBF is Greater than 1 Billion Years
 58. Synchronizer Chain #11: Typical MTBF is Greater than 1 Billion Years
 59. Synchronizer Chain #12: Typical MTBF is Greater than 1 Billion Years
 60. Synchronizer Chain #13: Typical MTBF is Greater than 1 Billion Years
 61. Synchronizer Chain #14: Typical MTBF is Greater than 1 Billion Years
 62. Synchronizer Chain #15: Typical MTBF is Greater than 1 Billion Years
 63. Synchronizer Chain #16: Typical MTBF is Greater than 1 Billion Years
 64. Synchronizer Chain #17: Typical MTBF is Greater than 1 Billion Years
 65. Synchronizer Chain #18: Typical MTBF is Greater than 1 Billion Years
 66. Synchronizer Chain #19: Typical MTBF is Greater than 1 Billion Years
 67. Synchronizer Chain #20: Typical MTBF is Greater than 1 Billion Years
 68. Synchronizer Chain #21: Typical MTBF is Greater than 1 Billion Years
 69. Synchronizer Chain #22: Typical MTBF is Greater than 1 Billion Years
 70. Synchronizer Chain #23: Typical MTBF is Greater than 1 Billion Years
 71. Synchronizer Chain #24: Typical MTBF is Greater than 1 Billion Years
 72. Synchronizer Chain #25: Typical MTBF is Greater than 1 Billion Years
 73. Synchronizer Chain #26: Typical MTBF is Greater than 1 Billion Years
 74. Synchronizer Chain #27: Typical MTBF is Greater than 1 Billion Years
 75. Synchronizer Chain #28: Typical MTBF is Greater than 1 Billion Years
 76. Synchronizer Chain #29: Typical MTBF is Greater than 1 Billion Years
 77. Synchronizer Chain #30: Typical MTBF is Greater than 1 Billion Years
 78. Synchronizer Chain #31: Typical MTBF is Greater than 1 Billion Years
 79. Synchronizer Chain #32: Typical MTBF is Greater than 1 Billion Years
 80. Synchronizer Chain #33: Typical MTBF is Greater than 1 Billion Years
 81. Synchronizer Chain #34: Typical MTBF is Greater than 1 Billion Years
 82. Synchronizer Chain #35: Typical MTBF is Greater than 1 Billion Years
 83. Synchronizer Chain #36: Typical MTBF is Greater than 1 Billion Years
 84. Synchronizer Chain #37: Typical MTBF is Greater than 1 Billion Years
 85. Synchronizer Chain #38: Typical MTBF is Greater than 1 Billion Years
 86. Synchronizer Chain #39: Typical MTBF is Greater than 1 Billion Years
 87. Synchronizer Chain #40: Typical MTBF is Greater than 1 Billion Years
 88. Synchronizer Chain #41: Typical MTBF is Greater than 1 Billion Years
 89. Synchronizer Chain #42: Typical MTBF is Greater than 1 Billion Years
 90. Synchronizer Chain #43: Typical MTBF is Greater than 1 Billion Years
 91. Synchronizer Chain #44: Typical MTBF is Greater than 1 Billion Years
 92. Synchronizer Chain #45: Typical MTBF is Greater than 1 Billion Years
 93. Synchronizer Chain #46: Typical MTBF is Greater than 1 Billion Years
 94. Synchronizer Chain #47: Typical MTBF is Greater than 1 Billion Years
 95. Synchronizer Chain #48: Typical MTBF is Greater than 1 Billion Years
 96. Synchronizer Chain #49: Typical MTBF is Greater than 1 Billion Years
 97. Synchronizer Chain #50: Typical MTBF is Greater than 1 Billion Years
 98. Synchronizer Chain #51: Typical MTBF is Greater than 1 Billion Years
 99. Synchronizer Chain #52: Typical MTBF is Greater than 1 Billion Years
100. Synchronizer Chain #53: Typical MTBF is Greater than 1 Billion Years
101. Synchronizer Chain #54: Typical MTBF is Greater than 1 Billion Years
102. Synchronizer Chain #55: Typical MTBF is Greater than 1 Billion Years
103. Synchronizer Chain #56: Typical MTBF is Greater than 1 Billion Years
104. Synchronizer Chain #57: Typical MTBF is Greater than 1 Billion Years
105. Synchronizer Chain #58: Typical MTBF is Greater than 1 Billion Years
106. Synchronizer Chain #59: Typical MTBF is Greater than 1 Billion Years
107. Synchronizer Chain #60: Typical MTBF is Greater than 1 Billion Years
108. Synchronizer Chain #61: Typical MTBF is Greater than 1 Billion Years
109. Synchronizer Chain #62: Typical MTBF is Greater than 1 Billion Years
110. Synchronizer Chain #63: Typical MTBF is Greater than 1 Billion Years
111. Synchronizer Chain #64: Typical MTBF is Greater than 1 Billion Years
112. Slow 1200mV 0C Model Fmax Summary
113. Slow 1200mV 0C Model Setup Summary
114. Slow 1200mV 0C Model Hold Summary
115. Slow 1200mV 0C Model Recovery Summary
116. Slow 1200mV 0C Model Removal Summary
117. Slow 1200mV 0C Model Minimum Pulse Width Summary
118. Slow 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
119. Slow 1200mV 0C Model Setup: 'CLOCK_50'
120. Slow 1200mV 0C Model Setup: 'altera_reserved_tck'
121. Slow 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
122. Slow 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
123. Slow 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
124. Slow 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
125. Slow 1200mV 0C Model Hold: 'CLOCK_50'
126. Slow 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
127. Slow 1200mV 0C Model Hold: 'altera_reserved_tck'
128. Slow 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
129. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
130. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'
131. Slow 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
132. Slow 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
133. Slow 1200mV 0C Model Removal: 'altera_reserved_tck'
134. Slow 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
135. Slow 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
136. Slow 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
137. Slow 1200mV 0C Model Removal: 'CLOCK_50'
138. Slow 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
139. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
140. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
141. Slow 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
142. Slow 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
143. Setup Times
144. Hold Times
145. Clock to Output Times
146. Minimum Clock to Output Times
147. Output Enable Times
148. Minimum Output Enable Times
149. Output Disable Times
150. Minimum Output Disable Times
151. MTBF Summary
152. Synchronizer Summary
153. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years
154. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years
155. Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years
156. Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years
157. Synchronizer Chain #5: Typical MTBF is Greater than 1 Billion Years
158. Synchronizer Chain #6: Typical MTBF is Greater than 1 Billion Years
159. Synchronizer Chain #7: Typical MTBF is Greater than 1 Billion Years
160. Synchronizer Chain #8: Typical MTBF is Greater than 1 Billion Years
161. Synchronizer Chain #9: Typical MTBF is Greater than 1 Billion Years
162. Synchronizer Chain #10: Typical MTBF is Greater than 1 Billion Years
163. Synchronizer Chain #11: Typical MTBF is Greater than 1 Billion Years
164. Synchronizer Chain #12: Typical MTBF is Greater than 1 Billion Years
165. Synchronizer Chain #13: Typical MTBF is Greater than 1 Billion Years
166. Synchronizer Chain #14: Typical MTBF is Greater than 1 Billion Years
167. Synchronizer Chain #15: Typical MTBF is Greater than 1 Billion Years
168. Synchronizer Chain #16: Typical MTBF is Greater than 1 Billion Years
169. Synchronizer Chain #17: Typical MTBF is Greater than 1 Billion Years
170. Synchronizer Chain #18: Typical MTBF is Greater than 1 Billion Years
171. Synchronizer Chain #19: Typical MTBF is Greater than 1 Billion Years
172. Synchronizer Chain #20: Typical MTBF is Greater than 1 Billion Years
173. Synchronizer Chain #21: Typical MTBF is Greater than 1 Billion Years
174. Synchronizer Chain #22: Typical MTBF is Greater than 1 Billion Years
175. Synchronizer Chain #23: Typical MTBF is Greater than 1 Billion Years
176. Synchronizer Chain #24: Typical MTBF is Greater than 1 Billion Years
177. Synchronizer Chain #25: Typical MTBF is Greater than 1 Billion Years
178. Synchronizer Chain #26: Typical MTBF is Greater than 1 Billion Years
179. Synchronizer Chain #27: Typical MTBF is Greater than 1 Billion Years
180. Synchronizer Chain #28: Typical MTBF is Greater than 1 Billion Years
181. Synchronizer Chain #29: Typical MTBF is Greater than 1 Billion Years
182. Synchronizer Chain #30: Typical MTBF is Greater than 1 Billion Years
183. Synchronizer Chain #31: Typical MTBF is Greater than 1 Billion Years
184. Synchronizer Chain #32: Typical MTBF is Greater than 1 Billion Years
185. Synchronizer Chain #33: Typical MTBF is Greater than 1 Billion Years
186. Synchronizer Chain #34: Typical MTBF is Greater than 1 Billion Years
187. Synchronizer Chain #35: Typical MTBF is Greater than 1 Billion Years
188. Synchronizer Chain #36: Typical MTBF is Greater than 1 Billion Years
189. Synchronizer Chain #37: Typical MTBF is Greater than 1 Billion Years
190. Synchronizer Chain #38: Typical MTBF is Greater than 1 Billion Years
191. Synchronizer Chain #39: Typical MTBF is Greater than 1 Billion Years
192. Synchronizer Chain #40: Typical MTBF is Greater than 1 Billion Years
193. Synchronizer Chain #41: Typical MTBF is Greater than 1 Billion Years
194. Synchronizer Chain #42: Typical MTBF is Greater than 1 Billion Years
195. Synchronizer Chain #43: Typical MTBF is Greater than 1 Billion Years
196. Synchronizer Chain #44: Typical MTBF is Greater than 1 Billion Years
197. Synchronizer Chain #45: Typical MTBF is Greater than 1 Billion Years
198. Synchronizer Chain #46: Typical MTBF is Greater than 1 Billion Years
199. Synchronizer Chain #47: Typical MTBF is Greater than 1 Billion Years
200. Synchronizer Chain #48: Typical MTBF is Greater than 1 Billion Years
201. Synchronizer Chain #49: Typical MTBF is Greater than 1 Billion Years
202. Synchronizer Chain #50: Typical MTBF is Greater than 1 Billion Years
203. Synchronizer Chain #51: Typical MTBF is Greater than 1 Billion Years
204. Synchronizer Chain #52: Typical MTBF is Greater than 1 Billion Years
205. Synchronizer Chain #53: Typical MTBF is Greater than 1 Billion Years
206. Synchronizer Chain #54: Typical MTBF is Greater than 1 Billion Years
207. Synchronizer Chain #55: Typical MTBF is Greater than 1 Billion Years
208. Synchronizer Chain #56: Typical MTBF is Greater than 1 Billion Years
209. Synchronizer Chain #57: Typical MTBF is Greater than 1 Billion Years
210. Synchronizer Chain #58: Typical MTBF is Greater than 1 Billion Years
211. Synchronizer Chain #59: Typical MTBF is Greater than 1 Billion Years
212. Synchronizer Chain #60: Typical MTBF is Greater than 1 Billion Years
213. Synchronizer Chain #61: Typical MTBF is Greater than 1 Billion Years
214. Synchronizer Chain #62: Typical MTBF is Greater than 1 Billion Years
215. Synchronizer Chain #63: Typical MTBF is Greater than 1 Billion Years
216. Synchronizer Chain #64: Typical MTBF is Greater than 1 Billion Years
217. Fast 1200mV 0C Model Setup Summary
218. Fast 1200mV 0C Model Hold Summary
219. Fast 1200mV 0C Model Recovery Summary
220. Fast 1200mV 0C Model Removal Summary
221. Fast 1200mV 0C Model Minimum Pulse Width Summary
222. Fast 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
223. Fast 1200mV 0C Model Setup: 'CLOCK_50'
224. Fast 1200mV 0C Model Setup: 'altera_reserved_tck'
225. Fast 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
226. Fast 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
227. Fast 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
228. Fast 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
229. Fast 1200mV 0C Model Hold: 'CLOCK_50'
230. Fast 1200mV 0C Model Hold: 'altera_reserved_tck'
231. Fast 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
232. Fast 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
233. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
234. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'
235. Fast 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
236. Fast 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
237. Fast 1200mV 0C Model Removal: 'altera_reserved_tck'
238. Fast 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
239. Fast 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
240. Fast 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
241. Fast 1200mV 0C Model Removal: 'CLOCK_50'
242. Fast 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'
243. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
244. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
245. Fast 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'
246. Fast 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'
247. Setup Times
248. Hold Times
249. Clock to Output Times
250. Minimum Clock to Output Times
251. Output Enable Times
252. Minimum Output Enable Times
253. Output Disable Times
254. Minimum Output Disable Times
255. MTBF Summary
256. Synchronizer Summary
257. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years
258. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years
259. Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years
260. Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years
261. Synchronizer Chain #5: Typical MTBF is Greater than 1 Billion Years
262. Synchronizer Chain #6: Typical MTBF is Greater than 1 Billion Years
263. Synchronizer Chain #7: Typical MTBF is Greater than 1 Billion Years
264. Synchronizer Chain #8: Typical MTBF is Greater than 1 Billion Years
265. Synchronizer Chain #9: Typical MTBF is Greater than 1 Billion Years
266. Synchronizer Chain #10: Typical MTBF is Greater than 1 Billion Years
267. Synchronizer Chain #11: Typical MTBF is Greater than 1 Billion Years
268. Synchronizer Chain #12: Typical MTBF is Greater than 1 Billion Years
269. Synchronizer Chain #13: Typical MTBF is Greater than 1 Billion Years
270. Synchronizer Chain #14: Typical MTBF is Greater than 1 Billion Years
271. Synchronizer Chain #15: Typical MTBF is Greater than 1 Billion Years
272. Synchronizer Chain #16: Typical MTBF is Greater than 1 Billion Years
273. Synchronizer Chain #17: Typical MTBF is Greater than 1 Billion Years
274. Synchronizer Chain #18: Typical MTBF is Greater than 1 Billion Years
275. Synchronizer Chain #19: Typical MTBF is Greater than 1 Billion Years
276. Synchronizer Chain #20: Typical MTBF is Greater than 1 Billion Years
277. Synchronizer Chain #21: Typical MTBF is Greater than 1 Billion Years
278. Synchronizer Chain #22: Typical MTBF is Greater than 1 Billion Years
279. Synchronizer Chain #23: Typical MTBF is Greater than 1 Billion Years
280. Synchronizer Chain #24: Typical MTBF is Greater than 1 Billion Years
281. Synchronizer Chain #25: Typical MTBF is Greater than 1 Billion Years
282. Synchronizer Chain #26: Typical MTBF is Greater than 1 Billion Years
283. Synchronizer Chain #27: Typical MTBF is Greater than 1 Billion Years
284. Synchronizer Chain #28: Typical MTBF is Greater than 1 Billion Years
285. Synchronizer Chain #29: Typical MTBF is Greater than 1 Billion Years
286. Synchronizer Chain #30: Typical MTBF is Greater than 1 Billion Years
287. Synchronizer Chain #31: Typical MTBF is Greater than 1 Billion Years
288. Synchronizer Chain #32: Typical MTBF is Greater than 1 Billion Years
289. Synchronizer Chain #33: Typical MTBF is Greater than 1 Billion Years
290. Synchronizer Chain #34: Typical MTBF is Greater than 1 Billion Years
291. Synchronizer Chain #35: Typical MTBF is Greater than 1 Billion Years
292. Synchronizer Chain #36: Typical MTBF is Greater than 1 Billion Years
293. Synchronizer Chain #37: Typical MTBF is Greater than 1 Billion Years
294. Synchronizer Chain #38: Typical MTBF is Greater than 1 Billion Years
295. Synchronizer Chain #39: Typical MTBF is Greater than 1 Billion Years
296. Synchronizer Chain #40: Typical MTBF is Greater than 1 Billion Years
297. Synchronizer Chain #41: Typical MTBF is Greater than 1 Billion Years
298. Synchronizer Chain #42: Typical MTBF is Greater than 1 Billion Years
299. Synchronizer Chain #43: Typical MTBF is Greater than 1 Billion Years
300. Synchronizer Chain #44: Typical MTBF is Greater than 1 Billion Years
301. Synchronizer Chain #45: Typical MTBF is Greater than 1 Billion Years
302. Synchronizer Chain #46: Typical MTBF is Greater than 1 Billion Years
303. Synchronizer Chain #47: Typical MTBF is Greater than 1 Billion Years
304. Synchronizer Chain #48: Typical MTBF is Greater than 1 Billion Years
305. Synchronizer Chain #49: Typical MTBF is Greater than 1 Billion Years
306. Synchronizer Chain #50: Typical MTBF is Greater than 1 Billion Years
307. Synchronizer Chain #51: Typical MTBF is Greater than 1 Billion Years
308. Synchronizer Chain #52: Typical MTBF is Greater than 1 Billion Years
309. Synchronizer Chain #53: Typical MTBF is Greater than 1 Billion Years
310. Synchronizer Chain #54: Typical MTBF is Greater than 1 Billion Years
311. Synchronizer Chain #55: Typical MTBF is Greater than 1 Billion Years
312. Synchronizer Chain #56: Typical MTBF is Greater than 1 Billion Years
313. Synchronizer Chain #57: Typical MTBF is Greater than 1 Billion Years
314. Synchronizer Chain #58: Typical MTBF is Greater than 1 Billion Years
315. Synchronizer Chain #59: Typical MTBF is Greater than 1 Billion Years
316. Synchronizer Chain #60: Typical MTBF is Greater than 1 Billion Years
317. Synchronizer Chain #61: Typical MTBF is Greater than 1 Billion Years
318. Synchronizer Chain #62: Typical MTBF is Greater than 1 Billion Years
319. Synchronizer Chain #63: Typical MTBF is Greater than 1 Billion Years
320. Synchronizer Chain #64: Typical MTBF is Greater than 1 Billion Years
321. Multicorner Timing Analysis Summary
322. Setup Times
323. Hold Times
324. Clock to Output Times
325. Minimum Clock to Output Times
326. Board Trace Model Assignments
327. Input Transition Times
328. Signal Integrity Metrics (Slow 1200mv 0c Model)
329. Signal Integrity Metrics (Slow 1200mv 85c Model)
330. Signal Integrity Metrics (Fast 1200mv 0c Model)
331. Setup Transfers
332. Hold Transfers
333. Recovery Transfers
334. Removal Transfers
335. Report TCCS
336. Report RSKM
337. Unconstrained Paths
338. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
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(including device programming or simulation files), and any 
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Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                       ;
+--------------------+--------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
; Revision Name      ; DE0_Nano                                                           ;
; Device Family      ; Cyclone IV E                                                       ;
; Device Name        ; EP4CE22F17C6                                                       ;
; Timing Models      ; Final                                                              ;
; Delay Model        ; Combined                                                           ;
; Rise/Fall Delays   ; Enabled                                                            ;
+--------------------+--------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.43        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;  14.3%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------+
; SDC File List                                                                                      ;
+----------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                                  ; Status ; Read at                  ;
+----------------------------------------------------------------+--------+--------------------------+
; DE0_Nano_SOPC/synthesis/submodules/altera_reset_controller.sdc ; OK     ; Wed Sep 25 10:23:16 2013 ;
; DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_cpu.sdc       ; OK     ; Wed Sep 25 10:23:16 2013 ;
; DE0_Nano.SDC                                                   ; OK     ; Wed Sep 25 10:23:16 2013 ;
+----------------------------------------------------------------+--------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------------------------+-----------+---------+-----------+--------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------------------+--------------------------------------------------------+
; Clock Name                                         ; Type      ; Period  ; Frequency ; Rise   ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                               ; Targets                                                ;
+----------------------------------------------------+-----------+---------+-----------+--------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------------------+--------------------------------------------------------+
; altera_reserved_tck                                ; Base      ; 100.000 ; 10.0 MHz  ; 0.000  ; 50.000  ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                      ; { altera_reserved_tck }                                ;
; CLOCK_50                                           ; Base      ; 20.000  ; 50.0 MHz  ; 0.000  ; 10.000  ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                      ; { CLOCK_50 }                                           ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Generated ; 10.000  ; 100.0 MHz ; 0.000  ; 5.000   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CLOCK_50 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0] ; { DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] } ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ; Generated ; 10.000  ; 100.0 MHz ; -1.666 ; 3.334   ; 50.00      ; 1         ; 2           ; -60.0 ;        ;           ;            ; false    ; CLOCK_50 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0] ; { DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] } ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Generated ; 100.000 ; 10.0 MHz  ; 0.000  ; 50.000  ; 50.00      ; 5         ; 1           ;       ;        ;           ;            ; false    ; CLOCK_50 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0] ; { DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] } ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Generated ; 500.000 ; 2.0 MHz   ; 0.000  ; 250.000 ; 50.00      ; 25        ; 1           ;       ;        ;           ;            ; false    ; CLOCK_50 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0] ; { DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] } ;
+----------------------------------------------------+-----------+---------+-----------+--------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------------------+--------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                       ;
+------------+-----------------+----------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                         ; Note ;
+------------+-----------------+----------------------------------------------------+------+
; 79.63 MHz  ; 79.63 MHz       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;      ;
; 99.64 MHz  ; 99.64 MHz       ; CLOCK_50                                           ;      ;
; 120.41 MHz ; 120.41 MHz      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;      ;
; 179.15 MHz ; 179.15 MHz      ; altera_reserved_tck                                ;      ;
; 210.3 MHz  ; 210.3 MHz       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;      ;
+------------+-----------------+----------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                          ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 1.695   ; 0.000         ;
; CLOCK_50                                           ; 9.964   ; 0.000         ;
; altera_reserved_tck                                ; 47.209  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 87.442  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 247.819 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                         ;
+----------------------------------------------------+-------+---------------+
; Clock                                              ; Slack ; End Point TNS ;
+----------------------------------------------------+-------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.233 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.342 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.356 ; 0.000         ;
; CLOCK_50                                           ; 0.357 ; 0.000         ;
; altera_reserved_tck                                ; 0.358 ; 0.000         ;
+----------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                       ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 2.275   ; 0.000         ;
; CLOCK_50                                           ; 15.840  ; 0.000         ;
; altera_reserved_tck                                ; 48.469  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 96.973  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 248.245 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                      ;
+----------------------------------------------------+-------+---------------+
; Clock                                              ; Slack ; End Point TNS ;
+----------------------------------------------------+-------+---------------+
; altera_reserved_tck                                ; 0.885 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.912 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 1.815 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 1.838 ; 0.000         ;
; CLOCK_50                                           ; 2.840 ; 0.000         ;
+----------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                            ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 4.695   ; 0.000         ;
; CLOCK_50                                           ; 9.489   ; 0.000         ;
; altera_reserved_tck                                ; 49.537  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 49.740  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 249.746 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                         ;
+-------+--------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                      ; To Node                                                                                                                       ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.695 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.077     ; 8.223      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.818      ;
; 2.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.840      ;
; 2.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.840      ;
; 2.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.840      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.101 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.810      ;
; 2.103 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.832      ;
; 2.103 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.832      ;
; 2.103 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.832      ;
; 2.132 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_line_field[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.072     ; 7.791      ;
; 2.146 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.071     ; 7.778      ;
; 2.146 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.071     ; 7.778      ;
; 2.146 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.071     ; 7.778      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 7.757      ;
; 2.154 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.081     ; 7.760      ;
; 2.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.081     ; 7.758      ;
; 2.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 7.776      ;
; 2.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 7.776      ;
; 2.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 7.776      ;
; 2.168 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.081     ; 7.746      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 7.759      ;
; 2.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.081     ; 7.735      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.731      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.729      ;
; 2.184 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.081     ; 7.730      ;
; 2.184 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.081     ; 7.730      ;
; 2.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.750      ;
; 2.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.750      ;
; 2.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.750      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.748      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.748      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.748      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.717      ;
; 2.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.736      ;
; 2.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.736      ;
; 2.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 7.736      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
; 2.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[11] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 7.706      ;
+-------+--------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                 ; To Node                                                                                                                                                                                                       ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 9.964  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 9.715      ;
; 10.100 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 9.579      ;
; 10.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 9.455      ;
; 10.279 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 9.400      ;
; 10.881 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 8.798      ;
; 10.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 8.771      ;
; 11.029 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 8.650      ;
; 11.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 8.602      ;
; 11.130 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 8.549      ;
; 11.486 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 8.447      ;
; 11.670 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.316     ; 8.009      ;
; 11.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|stop_cmd_r                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 8.086      ;
; 11.913 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|old_read                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 8.019      ;
; 11.975 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 8.027      ;
; 11.975 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_valid       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 7.957      ;
; 11.978 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 7.997      ;
; 12.100 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.902      ;
; 12.111 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.891      ;
; 12.114 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 7.861      ;
; 12.124 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.878      ;
; 12.235 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.767      ;
; 12.235 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.767      ;
; 12.236 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.766      ;
; 12.238 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 7.737      ;
; 12.260 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.742      ;
; 12.290 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.712      ;
; 12.293 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 7.682      ;
; 12.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.642      ;
; 12.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.631      ;
; 12.384 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.618      ;
; 12.415 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.587      ;
; 12.439 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.563      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.202      ;
; 12.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.507      ;
; 12.549 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.453      ;
; 12.550 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.452      ;
; 12.557 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.309     ; 7.129      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 7.066      ;
; 12.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 7.292      ;
; 12.695 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.307      ;
; 12.703 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.309     ; 6.983      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.942      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.794 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.306     ; 6.895      ;
; 12.820 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.182      ;
; 12.828 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.309     ; 6.858      ;
; 12.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.007      ; 7.150      ;
; 12.860 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.309     ; 6.826      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.005      ;
; 12.883 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|last_channel[0]                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 7.050      ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                                                                ; To Node                                                                                                                                                                                                                                                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 47.209 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.195      ; 2.981      ;
; 47.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.195      ; 2.782      ;
; 47.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.195      ; 2.724      ;
; 47.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.194      ; 2.539      ;
; 47.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.200      ; 2.535      ;
; 47.707 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.194      ; 2.482      ;
; 47.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.195      ; 2.226      ;
; 48.023 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 2.170      ;
; 48.044 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.204      ; 2.155      ;
; 48.047 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.184      ; 2.132      ;
; 48.099 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.195      ; 2.091      ;
; 48.102 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 2.091      ;
; 48.156 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.196      ; 2.035      ;
; 48.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 2.003      ;
; 48.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.194      ; 1.806      ;
; 48.419 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 1.774      ;
; 49.080 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 1.113      ;
; 49.327 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.197      ; 0.865      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.344      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.265      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.645 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.254      ;
; 95.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.236      ;
; 95.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.236      ;
; 95.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.205      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 4.181      ;
; 95.788 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 4.122      ;
; 95.803 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 4.108      ;
; 95.804 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 4.107      ;
; 95.841 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 4.070      ;
; 95.862 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.055      ;
; 95.862 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.055      ;
; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.052      ;
; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.052      ;
; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.052      ;
; 95.918 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 3.992      ;
; 95.918 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 3.992      ;
; 95.920 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.020      ;
; 95.920 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.020      ;
; 95.920 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.020      ;
; 95.920 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.020      ;
; 95.920 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.020      ;
; 95.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.920      ;
; 95.992 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.919      ;
; 95.992 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.919      ;
; 95.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.916      ;
; 95.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.913      ;
; 96.008 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.091     ; 3.896      ;
; 96.008 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.091     ; 3.896      ;
; 96.023 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.917      ;
; 96.023 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.917      ;
; 96.023 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.917      ;
; 96.023 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.917      ;
; 96.023 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.917      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.033 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.095     ; 3.867      ;
; 96.041 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 3.869      ;
; 96.117 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.794      ;
; 96.118 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.793      ;
; 96.155 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.756      ;
; 96.158 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 3.752      ;
; 96.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 3.731      ;
; 96.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.093     ; 3.716      ;
; 96.222 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 3.715      ;
; 96.222 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 3.715      ;
; 96.274 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.085     ; 3.636      ;
; 96.283 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 3.652      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                    ; To Node                                                                                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 87.442 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.313     ; 12.240     ;
; 88.303 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.313     ; 11.379     ;
; 88.641 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 11.297     ;
; 88.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 10.988     ;
; 89.099 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.313     ; 10.583     ;
; 89.334 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.313     ; 10.348     ;
; 89.395 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 10.542     ;
; 89.525 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.313     ; 10.157     ;
; 89.548 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.313     ; 10.134     ;
; 89.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 10.231     ;
; 89.815 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[5]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 10.125     ;
; 89.917 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 10.115     ;
; 90.046 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.986      ;
; 90.072 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.960      ;
; 90.286 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.746      ;
; 90.353 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.059     ; 9.583      ;
; 90.486 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[6]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 9.454      ;
; 90.499 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.533      ;
; 90.604 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 9.370      ;
; 90.647 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 9.294      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.692 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 9.180      ;
; 90.778 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.254      ;
; 90.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.125      ;
; 90.918 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.067     ; 9.010      ;
; 90.933 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 9.099      ;
; 90.942 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.202      ; 9.288      ;
; 90.942 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 8.998      ;
; 90.975 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.067     ; 8.953      ;
; 91.116 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.293      ; 9.172      ;
; 91.133 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.805      ;
; 91.147 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 8.885      ;
; 91.245 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.293      ; 9.043      ;
; 91.254 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.205      ; 8.979      ;
; 91.258 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[0]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.322     ; 8.415      ;
; 91.258 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[1]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.322     ; 8.415      ;
; 91.258 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[2]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.322     ; 8.415      ;
; 91.258 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[3]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.322     ; 8.415      ;
; 91.258 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[4]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.322     ; 8.415      ;
; 91.258 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.322     ; 8.415      ;
; 91.268 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 8.672      ;
; 91.271 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.293      ; 9.017      ;
; 91.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 8.672      ;
; 91.400 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 8.574      ;
; 91.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.296      ; 8.863      ;
; 91.438 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 8.503      ;
; 91.442 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.348     ; 8.205      ;
; 91.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.068     ; 8.478      ;
; 91.464 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 8.473      ;
; 91.478 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.068     ; 8.449      ;
; 91.485 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.293      ; 8.803      ;
; 91.511 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.427      ;
; 91.543 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.054     ; 8.398      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.319      ;
; 91.557 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.296      ; 8.734      ;
; 91.570 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 8.368      ;
; 91.574 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.037      ; 8.458      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                             ; To Node                                                                                                                                   ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 247.819 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 2.097      ;
; 247.819 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 2.097      ;
; 247.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 2.022      ;
; 248.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 1.810      ;
; 248.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 1.750      ;
; 248.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 1.749      ;
; 248.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 1.746      ;
; 248.385 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 1.531      ;
; 248.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 1.513      ;
; 248.530 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 1.386      ;
; 248.533 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 1.416      ;
; 248.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.069     ; 1.380      ;
; 248.559 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.069     ; 1.367      ;
; 248.665 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 1.251      ;
; 248.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.069     ; 1.086      ;
; 495.245 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 4.321      ;
; 495.518 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 4.414      ;
; 495.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 3.839      ;
; 496.038 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 3.528      ;
; 496.244 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 3.322      ;
; 496.244 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 3.322      ;
; 496.244 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 3.322      ;
; 496.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 3.222      ;
; 496.427 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.142      ;
; 496.427 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.142      ;
; 496.427 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.142      ;
; 496.427 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.142      ;
; 496.427 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.142      ;
; 496.427 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.142      ;
; 496.451 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.481      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 3.104      ;
; 496.544 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.388      ;
; 496.544 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.388      ;
; 496.544 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.388      ;
; 496.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.314      ;
; 496.644 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.288      ;
; 496.686 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 2.880      ;
; 496.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.208      ;
; 496.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.208      ;
; 496.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.208      ;
; 496.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.208      ;
; 496.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.208      ;
; 496.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.208      ;
; 496.739 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.181      ;
; 496.739 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.181      ;
; 496.742 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.178      ;
; 496.742 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.178      ;
; 496.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.177      ;
; 496.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.177      ;
; 496.749 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.171      ;
; 496.749 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.171      ;
; 496.750 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.170      ;
; 496.750 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.170      ;
; 496.754 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.166      ;
; 496.754 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.166      ;
; 496.755 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.165      ;
; 496.755 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.165      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.765 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.060     ; 3.170      ;
; 496.771 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.161      ;
; 496.773 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.159      ;
; 496.773 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.159      ;
; 496.773 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 3.159      ;
; 496.774 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.146      ;
; 496.774 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 3.146      ;
; 496.836 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 2.730      ;
; 496.836 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 2.730      ;
; 496.836 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.429     ; 2.730      ;
; 496.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.704      ;
; 496.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.704      ;
; 496.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.704      ;
; 496.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.704      ;
; 496.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.704      ;
; 496.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.704      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.426     ; 2.668      ;
; 496.945 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.975      ;
; 496.949 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.971      ;
; 496.951 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.969      ;
; 496.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.967      ;
; 496.954 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.966      ;
; 496.962 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.958      ;
; 496.962 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.075     ; 2.958      ;
; 496.976 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 2.956      ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                                                                              ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.233 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[30]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.803      ;
; 0.302 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[17]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.872      ;
; 0.307 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[5]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.384      ; 0.878      ;
; 0.310 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[29]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.880      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.382      ; 0.880      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 0.881      ;
; 0.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.382      ; 0.888      ;
; 0.321 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mem_baddr[11]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.891      ;
; 0.321 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mem_baddr[12]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.891      ;
; 0.322 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_data[3]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.384      ; 0.893      ;
; 0.322 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 0.890      ;
; 0.324 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[10]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.896      ;
; 0.324 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[16]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.896      ;
; 0.325 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[12]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.897      ;
; 0.328 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[14]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.900      ;
; 0.329 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[1]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.378      ; 0.894      ;
; 0.329 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[2]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.378      ; 0.894      ;
; 0.330 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[12]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.900      ;
; 0.332 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_data[16]                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.384      ; 0.903      ;
; 0.332 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[0]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.379      ; 0.898      ;
; 0.332 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[2]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.379      ; 0.898      ;
; 0.332 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[3]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.382      ; 0.901      ;
; 0.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[13]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.905      ;
; 0.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[27]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.906      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[15]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.911      ;
; 0.343 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.382      ; 0.912      ;
; 0.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[28]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.383      ; 0.914      ;
; 0.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 0.917      ;
; 0.351 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.385      ; 0.923      ;
; 0.353 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[4]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.382      ; 0.922      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.078      ; 0.591      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[0]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[0]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[2]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[2]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[2]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[2]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|empty                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|empty                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|full                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|full                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[1]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[1]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|pending_response_count[0]                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|pending_response_count[0]                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|has_pending_responses                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|has_pending_responses                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_offset[1]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_offset[1]                                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_read                                                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_read                                                                                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.078      ; 0.591      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_fill_has_started                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_fill_has_started                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.000                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.000                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[0]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[0]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[1]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[1]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[2]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[2]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[0]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[0]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[1]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[1]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[2]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[2]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.000                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.000                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.101                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.101                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.101                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.101                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|init_done                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|init_done                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|wr_address                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|wr_address                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000100                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000100                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[0]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[0]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[2]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[2]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|rd_address                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|rd_address                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_rd                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_rd                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_has_started                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_has_started                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[1]                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[1]                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[2]                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[2]                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[1]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[1]                                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[2]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[2]                                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_active                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_active                                                                                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[80]                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[80]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|count[0]                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|count[0]                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][83]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][83]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|resetlatch                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|resetlatch                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|MonDReg[25]                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|MonDReg[25]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_ram_rd                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_ram_rd                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_next.010000000                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_next.010000000                                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|ack_refresh_request                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|ack_refresh_request                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|refresh_request                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|refresh_request                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000001                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000001                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|active_cs_n                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|active_cs_n                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[0]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[0]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|address_reg[1]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|address_reg[1]                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][55]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][55]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][57]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][57]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[80][101]                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[80][101]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[48][101]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[48][101]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[1]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[1]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|use_reg                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|use_reg                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][82]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][82]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[1]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[1]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[2]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[2]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[0]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[0]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[7]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[7]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][47]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][47]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][66]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][66]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[10]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[10]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[4]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[4]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.063      ; 0.577      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                             ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.342 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.577      ;
; 0.342 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.577      ;
; 0.342 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.577      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.580      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.580      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.580      ;
; 0.367 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.602      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.594      ;
; 0.378 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.598      ;
; 0.392 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.612      ;
; 0.392 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.612      ;
; 0.392 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.612      ;
; 0.393 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.613      ;
; 0.394 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.613      ;
; 0.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.624      ;
; 0.406 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.625      ;
; 0.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.630      ;
; 0.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.631      ;
; 0.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.641      ;
; 0.499 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.719      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.735      ;
; 0.508 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 0.731      ;
; 0.515 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.734      ;
; 0.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.736      ;
; 0.517 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.736      ;
; 0.538 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.758      ;
; 0.551 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.771      ;
; 0.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.773      ;
; 0.555 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.775      ;
; 0.555 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.775      ;
; 0.555 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.775      ;
; 0.558 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.560 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.780      ;
; 0.569 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.789      ;
; 0.586 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.806      ;
; 0.586 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.806      ;
; 0.596 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.816      ;
; 0.598 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.817      ;
; 0.603 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.823      ;
; 0.606 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.826      ;
; 0.607 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.827      ;
; 0.607 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.827      ;
; 0.609 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.829      ;
; 0.610 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.830      ;
; 0.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.857      ;
; 0.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.862      ;
; 0.651 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.870      ;
; 0.651 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.870      ;
; 0.652 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.871      ;
; 0.666 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.886      ;
; 0.667 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.887      ;
; 0.671 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.429      ; 1.257      ;
; 0.686 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 0.921      ;
; 0.687 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.907      ;
; 0.689 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.909      ;
; 0.702 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 0.921      ;
; 0.707 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.429      ; 1.293      ;
; 0.716 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.936      ;
; 0.717 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.937      ;
; 0.719 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 0.939      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                          ; To Node                                                                                                                                                                                                            ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_select_i2c_clk:select_i2c_clk|data_out                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_select_i2c_clk:select_i2c_clk|data_out                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.577      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 0.593      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.580      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.580      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.580      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.580      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.580      ;
; 0.365 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 0.600      ;
; 0.370 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 0.605      ;
; 0.370 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 0.605      ;
; 0.370 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.590      ;
; 0.370 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.590      ;
; 0.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.591      ;
; 0.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.591      ;
; 0.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.591      ;
; 0.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.591      ;
; 0.372 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.592      ;
; 0.372 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[31]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[15]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.592      ;
; 0.372 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.592      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[27]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[11]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[20]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[4]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[10]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.594      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.594      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.594      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.594      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.595      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.595      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.595      ;
; 0.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|readdata[0]                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.598      ;
; 0.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.597      ;
; 0.378 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.598      ;
; 0.380 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.600      ;
; 0.380 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.599      ;
; 0.381 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.600      ;
; 0.381 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.600      ;
; 0.381 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.601      ;
; 0.381 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.601      ;
; 0.383 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.603      ;
; 0.389 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.610      ;
; 0.390 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.610      ;
; 0.394 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 0.615      ;
; 0.399 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.619      ;
; 0.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.630      ;
; 0.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.631      ;
; 0.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.631      ;
; 0.412 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.632      ;
; 0.413 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.633      ;
; 0.414 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.634      ;
; 0.415 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 0.634      ;
; 0.423 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 0.643      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                  ; To Node                                                                                                                                                                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.577      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.077      ; 0.592      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[1]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.078      ; 0.593      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.077      ; 0.592      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_primed                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_primed                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|transmitting                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|transmitting                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|SCLK_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|SCLK_reg                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|MISO_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|MISO_reg                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_RW                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_RW                                                                                                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_scl:i2c_scl|data_out                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_scl:i2c_scl|data_out                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_dir                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_dir                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|pfdena_reg                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|pfdena_reg                                                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_out                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_out                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|pending_response_count[0]                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|pending_response_count[0]                                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.077      ; 0.593      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.078      ; 0.594      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|s_readdata[0]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|s_readdata[0]                                                                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.077      ; 0.594      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 0.592      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|wait_latency_counter[0]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|wait_latency_counter[0]                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[0]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 0.593      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|slowcount[0]                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|slowcount[0]                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|state[4]                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|state[4]                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
; 0.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_rd_strobe                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.590      ;
; 0.372 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe4a[0]                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe5a[0]                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.591      ;
; 0.372 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.591      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.592      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.077      ; 0.608      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[9]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[8]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[8]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[1]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[1]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[11]                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[11]                                                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[7]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[7]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.593      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[0]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[0]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.594      ;
; 0.376 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.595      ;
; 0.376 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.595      ;
; 0.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.596      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                                                                         ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.077      ; 0.593      ;
; 0.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.359 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.577      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.580      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.580      ;
; 0.362 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.580      ;
; 0.372 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.590      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.592      ;
; 0.373 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.591      ;
; 0.374 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.592      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.593      ;
; 0.375 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.593      ;
; 0.375 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.593      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.595      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.594      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.594      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.594      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.594      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.594      ;
; 0.376 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.594      ;
; 0.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.595      ;
; 0.379 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.598      ;
; 0.380 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[37]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[36]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.076      ; 0.613      ;
; 0.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.598      ;
; 0.381 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.600      ;
; 0.381 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.599      ;
; 0.381 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.599      ;
; 0.381 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.599      ;
; 0.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.600      ;
; 0.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.600      ;
; 0.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.600      ;
; 0.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.600      ;
; 0.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.600      ;
; 0.383 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[0]                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.601      ;
; 0.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.601      ;
; 0.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.601      ;
; 0.383 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.601      ;
; 0.383 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.601      ;
; 0.383 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.601      ;
; 0.384 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.602      ;
; 0.390 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.609      ;
; 0.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.612      ;
; 0.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.612      ;
; 0.393 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.612      ;
; 0.393 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[14]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.612      ;
; 0.394 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.613      ;
; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.613      ;
; 0.395 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.613      ;
; 0.395 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.613      ;
; 0.396 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.614      ;
; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.621      ;
; 0.478 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.697      ;
; 0.479 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.697      ;
; 0.480 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.699      ;
; 0.484 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.702      ;
; 0.485 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.703      ;
; 0.491 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.709      ;
; 0.498 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[12]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.717      ;
; 0.499 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.718      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[11]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[10]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.719      ;
; 0.502 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[1]                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.077      ; 0.736      ;
; 0.503 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.721      ;
; 0.506 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.725      ;
; 0.506 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.725      ;
; 0.511 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.730      ;
; 0.511 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.729      ;
; 0.515 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.734      ;
; 0.517 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.736      ;
; 0.518 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.737      ;
; 0.519 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.738      ;
; 0.522 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[15]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.740      ;
; 0.523 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.742      ;
; 0.523 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.742      ;
; 0.524 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.742      ;
; 0.525 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.743      ;
; 0.525 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 0.743      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[21]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.098     ; 2.622      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[26]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[10]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[6]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[22]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.095     ; 2.624      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[18]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[2]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[14]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 2.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[30]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.103     ; 2.616      ;
; 6.756 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[10]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.168     ; 2.968      ;
; 6.756 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[13]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.168     ; 2.968      ;
; 6.756 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[11]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.168     ; 2.968      ;
; 6.756 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[14]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.168     ; 2.968      ;
; 6.757 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[9]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.168     ; 2.967      ;
; 6.757 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[8]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.168     ; 2.967      ;
; 6.771 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[7]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.171     ; 2.950      ;
; 6.772 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[12]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.171     ; 2.949      ;
; 6.772 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[2]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.170     ; 2.950      ;
; 6.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.220     ; 2.834      ;
; 6.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[0]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.220     ; 2.834      ;
; 6.839 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[10]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.970      ;
; 6.839 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[11]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.970      ;
; 6.839 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[13]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.970      ;
; 6.839 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[14]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.970      ;
; 6.839 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_bank[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.090     ; 2.969      ;
; 6.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.969      ;
; 6.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[2]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.969      ;
; 6.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[3]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.090     ; 2.968      ;
; 6.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[6]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.090     ; 2.968      ;
; 6.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[8]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.969      ;
; 6.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[9]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.969      ;
; 6.844 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.125     ; 2.931      ;
; 6.844 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.125     ; 2.931      ;
; 6.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[4]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.088     ; 2.956      ;
; 6.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[7]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.952      ;
; 6.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_bank[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.091     ; 2.953      ;
; 6.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[5]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.091     ; 2.952      ;
; 6.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[7]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.951      ;
; 6.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[2]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.091     ; 2.952      ;
; 6.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[12]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.951      ;
; 6.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_dqm[0]                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.951      ;
; 6.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_dqm[1]                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.951      ;
; 6.864 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[3]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.198     ; 2.830      ;
; 6.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[6]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.191     ; 2.833      ;
; 6.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[5]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.191     ; 2.833      ;
; 6.868 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[10]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.105     ; 2.927      ;
; 6.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[15]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.193     ; 2.829      ;
; 6.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[4]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.193     ; 2.829      ;
; 6.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[3]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.103     ; 2.927      ;
; 6.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[11]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.103     ; 2.927      ;
; 6.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[12]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.099     ; 2.931      ;
; 6.871 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.098     ; 2.931      ;
; 6.871 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[9]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.098     ; 2.931      ;
; 6.872 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[8]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.098     ; 2.930      ;
; 6.874 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[5]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.096     ; 2.930      ;
; 6.874 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[6]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.096     ; 2.930      ;
; 6.876 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[4]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.098     ; 2.926      ;
; 6.876 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[15]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.098     ; 2.926      ;
; 6.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.954      ;
; 6.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.954      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[66]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[64]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[38]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[39]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.102     ; 2.953      ;
; 6.941 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.094     ; 2.960      ;
; 6.941 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.094     ; 2.960      ;
; 6.941 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.961      ;
; 6.941 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.094     ; 2.960      ;
; 6.958 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.094     ; 2.943      ;
; 6.958 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.094     ; 2.943      ;
; 7.014 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_10                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.779      ;
; 7.014 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_11                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.779      ;
; 7.014 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_13                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.779      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|read_latency_shift_reg[0]                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 4.085      ;
; 15.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.073      ;
; 15.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.073      ;
; 15.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.073      ;
; 15.881 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.072     ; 4.042      ;
; 15.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.036      ;
; 15.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.036      ;
; 15.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|CMD_START                                                                                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.030      ;
; 15.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_WRITE                                                                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.030      ;
; 15.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.030      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.190      ; 4.052      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|parity4                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[0]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[3]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 3.806      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[1]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[2]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[0]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[0]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[1]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|llreq                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[0]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[2]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[3]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[3]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[3]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[3]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 3.806      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[2]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 3.810      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[1]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.126 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[0]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.809      ;
; 16.136 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.809      ;
; 16.136 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.809      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 3.812      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 3.812      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.807      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|parity5                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.807      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 3.812      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[0]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 3.812      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[2]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 3.812      ;
; 16.137 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[3]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.807      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 1.724      ;
; 48.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0        ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.198      ; 1.724      ;
; 48.508 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.194      ; 1.681      ;
; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.252      ;
; 97.925 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 2.006      ;
; 97.925 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 2.006      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 1.989      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.970 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.965      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.961      ;
; 97.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.955      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.030 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.904      ;
; 98.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.724      ;
; 98.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.724      ;
; 98.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.724      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.701      ;
; 98.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.701      ;
; 98.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.701      ;
; 98.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.701      ;
; 98.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.701      ;
; 98.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.701      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.679      ;
; 98.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.240      ;
; 98.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.240      ;
; 98.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.240      ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                  ; To Node                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 96.973 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[1]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.940      ;
; 96.973 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[3]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.940      ;
; 96.973 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[2]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.940      ;
; 96.973 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.940      ;
; 96.992 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.927      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.195      ; 2.952      ;
; 97.285 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.229      ; 2.939      ;
; 97.285 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.229      ; 2.939      ;
; 97.285 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.229      ; 2.939      ;
; 97.285 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.229      ; 2.939      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0]                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.095     ; 2.595      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.095     ; 2.595      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.095     ; 2.595      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.095     ; 2.595      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.095     ; 2.595      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.096     ; 2.594      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.095     ; 2.595      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[3]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.093     ; 2.597      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.092     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.595      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[14]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[30]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[14]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[13]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[29]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[13]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[13]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[12]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[12]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[10]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.084     ; 2.598      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.078     ; 2.604      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.595      ;
; 97.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.087     ; 2.594      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 248.245 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.079     ; 1.671      ;
; 497.633 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.077     ; 2.285      ;
; 497.633 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.077     ; 2.285      ;
; 497.633 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.077     ; 2.285      ;
; 497.633 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.077     ; 2.285      ;
; 497.885 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 2.048      ;
; 497.885 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 2.048      ;
; 497.885 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 2.048      ;
; 497.885 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 2.048      ;
; 497.885 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 2.048      ;
; 497.885 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 2.048      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 497.965 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.971      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.020 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.916      ;
; 498.190 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.053     ; 1.752      ;
; 498.190 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.053     ; 1.752      ;
; 498.190 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.053     ; 1.752      ;
; 498.190 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.053     ; 1.752      ;
; 498.190 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.053     ; 1.752      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.729      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.699      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.059     ; 1.673      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.412      ;
; 498.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.289      ; 1.673      ;
; 498.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.289      ; 1.673      ;
; 498.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.289      ; 1.673      ;
; 498.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.289      ; 1.673      ;
; 498.644 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 1.288      ;
; 498.644 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 1.288      ;
; 498.644 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 1.288      ;
; 498.644 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.063     ; 1.288      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
; 498.662 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.062     ; 1.271      ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.885  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.104      ;
; 0.885  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.104      ;
; 0.885  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.104      ;
; 1.322  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.543      ;
; 1.322  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.543      ;
; 1.322  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.543      ;
; 1.322  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.543      ;
; 1.322  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.323  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.543      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.328  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.546      ;
; 1.331  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.552      ;
; 1.331  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.552      ;
; 1.331  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.552      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.538  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.757      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.568  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.788      ;
; 1.577  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.794      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.592  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.813      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.594  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.806      ;
; 1.619  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.836      ;
; 1.619  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.836      ;
; 1.853  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.075      ;
; 51.046 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.318      ; 1.541      ;
; 51.053 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate         ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.322      ; 1.552      ;
; 51.053 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0        ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.322      ; 1.552      ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.912 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.062      ; 1.131      ;
; 0.914 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.134      ;
; 0.914 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.134      ;
; 0.914 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.134      ;
; 0.914 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.134      ;
; 0.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.429      ; 1.539      ;
; 0.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.429      ; 1.539      ;
; 0.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.429      ; 1.539      ;
; 0.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.429      ; 1.539      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.274      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.539      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.553      ;
; 1.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.072      ; 1.568      ;
; 1.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.072      ; 1.568      ;
; 1.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.072      ; 1.568      ;
; 1.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.072      ; 1.568      ;
; 1.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.072      ; 1.568      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.350 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.573      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.554 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.066      ; 1.777      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.593 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.065      ; 1.815      ;
; 1.648 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.868      ;
; 1.648 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.868      ;
; 1.648 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.868      ;
; 1.648 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.868      ;
; 1.648 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.868      ;
; 1.648 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.063      ; 1.868      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 2.058      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.078      ; 2.058      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                             ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.815 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.420      ;
; 1.815 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.420      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.448      ; 2.427      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.440      ; 2.420      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[3]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.440      ; 2.420      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[4]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.440      ; 2.420      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.440      ; 2.420      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.440      ; 2.420      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.447      ; 2.427      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.447      ; 2.427      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[4]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.447      ; 2.427      ;
; 1.823 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[5]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.447      ; 2.427      ;
; 1.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.423      ; 2.420      ;
; 1.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.423      ; 2.420      ;
; 1.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.434      ; 2.433      ;
; 1.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.434      ; 2.433      ;
; 1.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq4                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.434      ; 2.433      ;
; 1.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq2                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.434      ; 2.433      ;
; 1.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq5                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.434      ; 2.433      ;
; 1.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq3                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.434      ; 2.433      ;
; 1.848 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[1]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.427      ; 2.432      ;
; 1.848 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[2]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.427      ; 2.432      ;
; 1.848 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[3]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.427      ; 2.432      ;
; 1.848 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[4]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.427      ; 2.432      ;
; 1.848 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[0]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.427      ; 2.432      ;
; 1.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.417      ; 2.423      ;
; 1.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.417      ; 2.423      ;
; 1.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.417      ; 2.423      ;
; 1.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.417      ; 2.423      ;
; 1.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.417      ; 2.423      ;
; 1.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.417      ; 2.423      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_valid                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.411      ; 2.425      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[11]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.411      ; 2.425      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[10]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.411      ; 2.425      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.410      ; 2.424      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.410      ; 2.424      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.410      ; 2.424      ;
; 1.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.410      ; 2.424      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.390      ; 2.741      ;
; 2.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.390      ; 2.741      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq0                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_offset[0]                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_offset[1]                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_offset[2]                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[12]                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.424      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[12]                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.424      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_extra_pc[12]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.424      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[13]                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.424      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_extra_pc[13]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.424      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|last_dest_id[1]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|pending_response_count[0]                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|has_pending_responses                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|last_dest_id[2]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_offset[1]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_offset[2]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[14]                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.424      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[6]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[7]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[8]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[17]                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_001|has_pending_responses                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[5]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[4]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.070      ; 2.429      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter|last_channel[0]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_cnt[0]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_cnt[1]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_cnt[2]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_cnt[3]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_read                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq4                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq2                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq1                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq5                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq0                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq3                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.069      ; 2.428      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_ap_offset[0]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_starting                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_starting                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.071      ; 2.430      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[9]                                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.061      ; 2.421      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_regnum_a_cmp_D                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.425      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_regnum_a_cmp_D                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.425      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|W_regnum_a_cmp_D                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.425      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_regnum_b_cmp_D                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.425      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_regnum_b_cmp_D                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.425      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|W_regnum_b_cmp_D                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.065      ; 2.425      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_ctrl_exception                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.062      ; 2.422      ;
; 2.203 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_ctrl_late_result                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.068      ; 2.428      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                                                                            ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.430      ; 2.425      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.425      ; 2.420      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.425      ; 2.420      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.425      ; 2.420      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.425      ; 2.420      ;
; 1.838 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.425      ; 2.420      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.060      ; 2.404      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[3]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.060      ; 2.404      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.060      ; 2.404      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.060      ; 2.404      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.070      ; 2.414      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.060      ; 2.404      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[16]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[17]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[18]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[19]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[20]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[21]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[22]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[23]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[24]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[25]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[26]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[27]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[28]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[29]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[30]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_is_running                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[31]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.416      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[14]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[30]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[14]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[13]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[29]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[13]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[13]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[12]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[12]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[10]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.412      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[10]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[10]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.073      ; 2.417      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[9]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.412      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[25]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[9]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[9]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[24]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[8]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.412      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[8]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[8]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 2.413      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[7]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[7]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[23]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[7]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[7]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[6]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[6]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.412      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[22]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[6]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[6]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[5]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[5]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.412      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[5]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[5]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.075      ; 2.419      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[4]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.412      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 2.422      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 2.422      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 2.422      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[1]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 2.422      ;
; 2.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.078      ; 2.422      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 2.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.456      ; 3.453      ;
; 2.840 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.456      ; 3.453      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.457      ; 3.466      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.457      ; 3.466      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.457      ; 3.466      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[38]                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|prev_reset                                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe6a[0]                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.445      ; 3.454      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[4]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 2.866 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.433      ; 3.456      ;
; 3.018 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|spi_clk                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.285      ; 3.460      ;
; 3.222 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe4a[0]                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 3.450      ;
; 3.222 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe5a[0]                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 3.450      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[1]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[2]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[3]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[4]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[5]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[6]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[7]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.231 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[0]                                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[0]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[1]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[2]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[3]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[4]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[5]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[6]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|full                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[31]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[26]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[25]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[24]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[19]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[16]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|wr_strobe                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_wr_strobe                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[15]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.454      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[9]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iEOP_reg                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[2]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[0]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[0]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[1]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[1]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[2]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[3]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[3]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[3]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[2]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[3]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[2]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[5]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[4]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[4]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[5]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[5]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[4]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[4]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[5]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[0]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[1]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[1]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[0]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[6]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[6]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[6]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[7]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[6]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 3.450      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[7]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 3.449      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[7]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[7]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.448      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[9]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 3.453      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_rd_strobe                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
; 3.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 3.452      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                                                                                                                                                                              ;
+-------+--------------+----------------+------------------+----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[16]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[17]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[18]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[19]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[20]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[21]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[22]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[23]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[24]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[25]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[26]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[27]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[28]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[29]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[30]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[31]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[0]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[10]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[11]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[12]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[13]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[14]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[15]                                                                                                                                                                                                                                                                               ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[1]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[2]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[3]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[4]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[5]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[6]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[7]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[8]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[9]                                                                                                                                                                                                                                                                                ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[0]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[10] ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[11] ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[12] ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[13] ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[14] ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[15] ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[1]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[2]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[3]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[4]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[5]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[6]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[7]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[8]  ;
; 4.695 ; 4.989        ; 0.294          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[9]  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[0]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[10]                                                                                                                                                                                                                                                                               ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[11]                                                                                                                                                                                                                                                                               ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[12]                                                                                                                                                                                                                                                                               ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[13]                                                                                                                                                                                                                                                                               ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[14]                                                                                                                                                                                                                                                                               ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[15]                                                                                                                                                                                                                                                                               ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[1]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[2]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[3]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[4]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[5]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[6]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[7]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[8]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[9]                                                                                                                                                                                                                                                                                ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[0]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[10]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[11]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[12]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[13]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[14]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[15]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[1]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[2]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[3]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[4]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[5]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[6]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[7]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[8]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[9]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[0]  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[10] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[11] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[12] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[13] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[14] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[15] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[16] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[17] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[18] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[19] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[1]  ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[20] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[21] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[22] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[23] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[24] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[25] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[26] ;
; 4.696 ; 4.990        ; 0.294          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[27] ;
+-------+--------------+----------------+------------------+----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                                                                                                                                                                                ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                                                                                                                                                                             ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.489 ; 9.719        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|altsyncram:the_boot_copier_rom|altsyncram_u341:auto_generated|ram_block1a0~porta_address_reg0                                                             ;
; 9.490 ; 9.720        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_address_reg0      ;
; 9.490 ; 9.720        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_datain_reg0       ;
; 9.490 ; 9.720        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_we_reg            ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                          ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                           ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                           ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                           ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                           ;
; 9.501 ; 9.731        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                           ;
; 9.503 ; 9.733        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0      ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[4]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                             ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; 9.582 ; 9.766        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe6a[0]                                    ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|prev_reset                                                                                                                               ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                   ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                  ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                      ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                      ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[38]                                                                     ;
; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                                                     ;
; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                     ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                    ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                     ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_rd_strobe                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[0]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[1]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[2]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[6]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[8]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_wr_strobe                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[0]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[1]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[2]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[3]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[4]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[5]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[7]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[8]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[9]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iEOP_reg                                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iE_reg                                                                                                  ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iROE_reg                                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iRRDY_reg                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iTOE_reg                                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iTRDY_reg                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|wr_strobe                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|CMD_START                                                                                                                                           ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_WRITE                                                                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_ADDR[0]                                                                                                                                         ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_ADDR[1]                                                                                                                                         ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_ADDR[2]                                                                                                                                         ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_ADDR[3]                                                                                                                                         ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.537 ; 49.753       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ;
; 49.537 ; 49.753       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0                                                                                                                                                                                                                         ;
; 49.537 ; 49.753       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                                                                               ;
; 49.575 ; 49.759       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ;
; 49.575 ; 49.759       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ;
; 49.575 ; 49.759       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[1]                                                    ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30]                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                                                                                                                                                                    ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                                                                                                                                                                    ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                                                                                    ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                                                                                                                                                                       ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]                                                                                                                                                                                                                                                                ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                                                                                                                                                                ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]                                                                                                                                                                                                                                                                ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]                                                                                                                                                                                                                                                           ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]                                                                                                                                                                                                                                                           ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]                                                                                                                                                                                                                                                           ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]                                                                                                                                                                                                                                                           ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                                                                                                                                                           ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                                                                                                                                                               ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                                                                                                                                                               ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                                                                                                                                                                ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                                                                                                                                                                ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ;
; 49.585 ; 49.769       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.000                                                   ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.010                                                   ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.100                                                   ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[0]                                                    ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[10]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[11]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[12]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[14]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[15]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[1]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[2]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[33]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[34]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[35]                                                       ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[3]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[4]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[5]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[6]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[8]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[9]                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav                                                                                                                                                                                                                        ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                                                                                      ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                                                                      ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]                                                                                                                                                                                                                         ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ;
; 49.586 ; 49.770       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.740 ; 49.970       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~porta_address_reg0      ;
; 49.740 ; 49.970       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~porta_datain_reg0       ;
; 49.740 ; 49.970       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~porta_we_reg            ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                                                                                                  ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                                                                                                  ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                                                                                                  ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                                                                                                  ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[3]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                              ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                              ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                              ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                              ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[0]                                                                                                                                                  ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                                                                                                  ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[2]                                                                                                                                                  ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[3]                                                                                                                                                  ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                                                                                                ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                       ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                         ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                         ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                         ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                         ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|read_latency_shift_reg[0]                                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0]                                                                                          ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                            ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                            ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                  ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[3]                                                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                                                                                        ;
; 49.747 ; 49.963       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                              ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                              ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                              ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                              ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                              ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                            ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                            ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[0]                                                                                                                                                ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[1]                                                                                                                                                ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[1]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[2]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[3]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_is_running                                                                                                                                     ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[10]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[12]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[13]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[14]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[22]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[23]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[24]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[25]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[29]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[30]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[4]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[5]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[6]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[7]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[8]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[9]                                                                                                                                    ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|delayed_unxcounter_is_zeroxx0                                                                                                                          ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                                                                                           ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[16]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[17]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[18]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[19]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[20]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[21]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[22]                                                                                                                                   ;
; 49.750 ; 49.966       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[23]                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                      ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ;
; 249.746 ; 249.962      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                     ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                     ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ;
; 249.747 ; 249.963      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ;
; 249.748 ; 249.964      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                 ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; 1.776 ; 2.279 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 1.918 ; 2.474 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; 1.087 ; 1.338 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 1.087 ; 1.338 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 1.087 ; 1.338 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 1.051 ; 1.301 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 1.080 ; 1.331 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 1.075 ; 1.326 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 1.073 ; 1.324 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 1.073 ; 1.324 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 1.052 ; 1.302 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 1.052 ; 1.302 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 1.075 ; 1.326 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; 2.830 ; 3.014 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; 4.543 ; 5.103 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; 4.543 ; 5.103 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; 2.658 ; 2.949 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; 3.210 ; 3.391 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; 2.916 ; 3.160 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; 2.925 ; 3.088 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; 3.210 ; 3.391 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; 2.882 ; 3.164 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; 2.025 ; 2.251 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; 2.992 ; 3.232 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; 7.505 ; 7.654 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; -1.395 ; -1.875 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; -1.486 ; -2.002 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; -0.559 ; -0.810 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; -0.559 ; -0.810 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; -0.526 ; -0.777 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; -0.552 ; -0.803 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; -0.546 ; -0.797 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; -0.545 ; -0.796 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; -0.545 ; -0.796 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; -0.527 ; -0.778 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; -0.528 ; -0.779 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; -0.524 ; -0.775 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; -0.546 ; -0.797 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; -1.880 ; -2.033 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; -1.333 ; -1.574 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; -3.397 ; -3.926 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; -1.333 ; -1.574 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; -1.552 ; -1.781 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; -1.587 ; -1.782 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; -1.854 ; -1.997 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; -1.865 ; -1.998 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; -1.552 ; -1.781 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; -1.203 ; -1.394 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; -0.022 ; -0.242 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; -2.016 ; -2.168 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                         ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 6.815  ; 6.843  ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 5.815  ; 5.885  ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 7.979  ; 7.901  ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 9.144  ; 9.004  ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 7.529  ; 7.410  ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 2.831  ; 2.744  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 2.828  ; 2.741  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 2.818  ; 2.736  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 2.938  ; 2.853  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 2.940  ; 2.855  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 2.816  ; 2.734  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 2.828  ; 2.741  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 2.945  ; 2.860  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 4.850  ; 4.486  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 2.947  ; 2.862  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 2.933  ; 2.848  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 2.933  ; 2.848  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 2.828  ; 2.741  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 2.813  ; 2.731  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 2.947  ; 2.862  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 2.947  ; 2.862  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 2.827  ; 2.740  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 2.945  ; 2.860  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 2.942  ; 2.857  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; 0.856  ;        ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;        ; 0.758  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 6.503  ; 6.461  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 7.681  ; 7.573  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 4.603  ; 4.579  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 5.117  ; 5.117  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 5.392  ; 5.378  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 4.275  ; 4.222  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 5.220  ; 5.379  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 7.681  ; 7.573  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 5.282  ; 5.330  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 6.918  ; 6.656  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 4.727  ; 4.639  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 5.306  ; 5.132  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 4.529  ; 4.491  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;        ; 4.178  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 11.688 ; 12.232 ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                               ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 6.598 ; 6.623 ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 5.613 ; 5.682 ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 6.841 ; 6.822 ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 7.191 ; 7.067 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 7.019 ; 6.884 ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 2.416 ; 2.334 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 2.544 ; 2.459 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 2.429 ; 2.342 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 2.431 ; 2.344 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 2.428 ; 2.341 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 2.429 ; 2.342 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 2.427 ; 2.340 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 2.417 ; 2.335 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 2.544 ; 2.459 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 2.537 ; 2.452 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 2.539 ; 2.454 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 2.416 ; 2.334 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 2.428 ; 2.341 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 2.428 ; 2.341 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 2.429 ; 2.342 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 2.544 ; 2.459 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 4.450 ; 4.086 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 2.412 ; 2.330 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 2.532 ; 2.447 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 2.532 ; 2.447 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 2.428 ; 2.341 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 2.412 ; 2.330 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 2.544 ; 2.459 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 2.546 ; 2.461 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 2.546 ; 2.461 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 2.427 ; 2.340 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 2.427 ; 2.340 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 2.430 ; 2.343 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 2.544 ; 2.459 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 2.427 ; 2.340 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 2.427 ; 2.340 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 2.427 ; 2.340 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 2.544 ; 2.459 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 2.541 ; 2.456 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; 0.407 ;       ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;       ; 0.309 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 5.789 ; 5.715 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 3.747 ; 3.692 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 4.062 ; 4.035 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 4.555 ; 4.551 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 4.819 ; 4.802 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 3.747 ; 3.692 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 4.657 ; 4.806 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 7.095 ; 6.978 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 4.711 ; 4.754 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 6.362 ; 6.097 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 4.025 ; 4.052 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 3.770 ; 4.528 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 3.991 ; 3.950 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;       ; 3.659 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 9.427 ; 9.972 ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                         ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 6.840 ; 6.718 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.646 ; 2.517 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.762 ; 2.640 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.762 ; 2.640 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.652 ; 2.519 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.646 ; 2.526 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.775 ; 2.653 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.776 ; 2.654 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.776 ; 2.654 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.651 ; 2.518 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.654 ; 2.521 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.654 ; 2.521 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.654 ; 2.521 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.654 ; 2.521 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.650 ; 2.517 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.654 ; 2.521 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.654 ; 2.521 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.775 ; 2.653 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                 ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 6.547 ; 6.425 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.247 ; 2.120 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.363 ; 2.241 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.363 ; 2.241 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.254 ; 2.121 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.247 ; 2.127 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.375 ; 2.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.377 ; 2.255 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.377 ; 2.255 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.253 ; 2.120 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.256 ; 2.123 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.256 ; 2.123 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.256 ; 2.123 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.256 ; 2.123 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.253 ; 2.120 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.256 ; 2.123 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.256 ; 2.123 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.375 ; 2.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 6.840     ; 6.962     ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.551     ; 2.684     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.698     ; 2.820     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.698     ; 2.820     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.553     ; 2.686     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.584     ; 2.704     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.711     ; 2.833     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.712     ; 2.834     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.712     ; 2.834     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.552     ; 2.685     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.555     ; 2.688     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.555     ; 2.688     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.555     ; 2.688     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.555     ; 2.688     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.551     ; 2.684     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.555     ; 2.688     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.555     ; 2.688     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.711     ; 2.833     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                        ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 6.517     ; 6.639     ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.153     ; 2.286     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.296     ; 2.418     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.296     ; 2.418     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.154     ; 2.287     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.182     ; 2.302     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.308     ; 2.430     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.310     ; 2.432     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.310     ; 2.432     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.153     ; 2.286     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.156     ; 2.289     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.156     ; 2.289     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.156     ; 2.289     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.156     ; 2.289     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.153     ; 2.286     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.156     ; 2.289     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.156     ; 2.289     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.308     ; 2.430     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+


----------------
; MTBF Summary ;
----------------
Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.

Number of Synchronizer Chains Found: 64
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
Worst Case Available Settling Time: 14.700 ns

Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+
; Source Node                                                                                                                                                                                              ; Synchronization Node                                                                                                                                                                                                                                                                                                                                                 ; Typical MTBF (Years)   ; Included in Design MTBF ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
;                                                                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                ; Greater than 1 Billion ; Yes                     ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ; Greater than 1 Billion ; Yes                     ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                              ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1       ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1       ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+


Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 14.700                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                              ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 8.881        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 5.819        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 14.822                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 0.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 8.883        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 5.939        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                       ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                       ; 15.193                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                          ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                          ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 8.951        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 6.242        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 15.530                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 0.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 8.959        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 6.571        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #5: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                   ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                 ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ;                                                                                                                                                                                                                                                       ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                   ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                   ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                            ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                            ; 18.472                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                               ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                     ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                   ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                     ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1  ;                        ;              ;                  ; 9.242        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ;                        ;              ;                  ; 9.230        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #6: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                    ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                           ; 18.474                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                              ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                                   ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                      ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1  ;                        ;              ;                  ; 9.243        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ;                        ;              ;                  ; 9.231        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #7: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                    ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                           ; 18.478                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                              ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                                   ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                      ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1  ;                        ;              ;                  ; 9.244        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ;                        ;              ;                  ; 9.234        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #8: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.204                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 6.742        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #9: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 25.225                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 8.883        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.246        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 7.096        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #10: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 25.328                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.229        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.085        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 7.014        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #11: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.395                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 9.245        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 9.247        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 6.903        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #12: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.404                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;                        ;              ;                  ; 9.244        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;                        ;              ;                  ; 9.247        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|dreg[1] ;                        ;              ;                  ; 6.913        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #13: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 25.515                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.232        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.052        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #14: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.600                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.246        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.098        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.256        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #15: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 25.762                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 8.882        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.099        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.781        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #16: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.767                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.230        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.232        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 7.305        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #17: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 25.779                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 9.227        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 9.085        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 7.467        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #18: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.956                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.087        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 7.638        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #19: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.025                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 8.858        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.100        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 8.067        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #20: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.087                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.230        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.086        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.771        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #21: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 26.293                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.085        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 7.977        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #22: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 26.351                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 8.879        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.098        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.374        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #23: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                     ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                   ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                             ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                                                     ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                     ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                              ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                              ; 26.356                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                 ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                       ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                       ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.229        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.229        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 7.898        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #24: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.388                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.230        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.087        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.071        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #25: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.422                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.083        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 8.108        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #26: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                           ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 26.504                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|edge_capture                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.244        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.246        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.014        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #27: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.611                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 8.857        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.099        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.655        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #28: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 26.706                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 8.881        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.246        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.579        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #29: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.915                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 8.854        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.098        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.963        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #30: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.921                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 8.857        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.102        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 8.962        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #31: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 26.946                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 8.879        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.101        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 8.966        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #32: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.962                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.231        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.230        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.501        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #33: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 26.967                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.232        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.227        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.508        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #34: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 27.316                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[0]                                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.243        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.243        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.830        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #35: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 27.447                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                     ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.228        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.230        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.989        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #36: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 36.446                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                              ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 19.101       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 17.345       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #37: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                       ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                       ; 36.698                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                          ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 19.232       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 17.466       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #38: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 54.175                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 19.232       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 18.855       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 16.088       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #39: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 54.304                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 19.229       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 18.855       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 16.220       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #40: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 54.493                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 18.855       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 19.099       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 16.539       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #41: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 54.549                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;                        ;              ;                  ; 19.232       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;                        ;              ;                  ; 18.853       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[1] ;                        ;              ;                  ; 16.464       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #42: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 55.358                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 19.228       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 18.853       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 17.277       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #43: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 55.593                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 18.854       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 19.103       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 17.636       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #44: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 55.627                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 19.229       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 18.852       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 17.546       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #45: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 55.722                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 19.233       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 19.089       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 17.400       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #46: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 55.772                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 19.247       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 19.244       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 17.281       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #47: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 56.059                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 19.232       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 19.086       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 17.741       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #48: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.304                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 19.246       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 19.097       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 18.961       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #49: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.455                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 19.245       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 19.245       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 18.965       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #50: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                          ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                                                                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                         ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                         ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                            ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                             ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                     ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                     ; 197.039                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                        ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                              ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                             ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ;                        ;              ;                  ; 99.231       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ;                        ;              ;                  ; 97.808       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #51: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                          ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready                                                                                                                                                       ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                         ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                         ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                            ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                             ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                     ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                     ; 198.026                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                        ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                              ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                             ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ;                        ;              ;                  ; 99.245       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ;                        ;              ;                  ; 98.781       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #52: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 294.686                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 98.882       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 99.242       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 96.562       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #53: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 294.716                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 98.878       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 99.247       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 96.591       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #54: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 294.893                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 98.881       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 99.099       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 96.913       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #55: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 294.970                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 98.880       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 99.243       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 96.847       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #56: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 295.309                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 98.883       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 99.242       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 97.184       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #57: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 295.339                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 99.230       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 99.086       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 97.023       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #58: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 295.628                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 98.878       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 99.241       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 97.509       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #59: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 295.846                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 98.881       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 99.099       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 97.866       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #60: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 296.720                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 99.246       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 99.101       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 98.373       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #61: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.035                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 99.247       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 99.099       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 98.689       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #62: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.729                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 99.244       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 99.243       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 99.242       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #63: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 995.124                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 499.086      ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 496.038      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #64: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 996.381                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 499.099      ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 497.282      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



+------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                        ;
+------------+-----------------+----------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                         ; Note ;
+------------+-----------------+----------------------------------------------------+------+
; 88.68 MHz  ; 88.68 MHz       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;      ;
; 110.47 MHz ; 110.47 MHz      ; CLOCK_50                                           ;      ;
; 133.74 MHz ; 133.74 MHz      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;      ;
; 204.75 MHz ; 204.75 MHz      ; altera_reserved_tck                                ;      ;
; 233.1 MHz  ; 233.1 MHz       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;      ;
+------------+-----------------+----------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                           ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 2.523   ; 0.000         ;
; CLOCK_50                                           ; 10.948  ; 0.000         ;
; altera_reserved_tck                                ; 47.558  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 88.724  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 248.036 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                          ;
+----------------------------------------------------+-------+---------------+
; Clock                                              ; Slack ; End Point TNS ;
+----------------------------------------------------+-------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.232 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.299 ; 0.000         ;
; CLOCK_50                                           ; 0.311 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.311 ; 0.000         ;
; altera_reserved_tck                                ; 0.311 ; 0.000         ;
+----------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                        ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 2.577   ; 0.000         ;
; CLOCK_50                                           ; 16.331  ; 0.000         ;
; altera_reserved_tck                                ; 48.703  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 97.319  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 248.437 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+----------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                       ;
+----------------------------------------------------+-------+---------------+
; Clock                                              ; Slack ; End Point TNS ;
+----------------------------------------------------+-------+---------------+
; altera_reserved_tck                                ; 0.791 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.822 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 1.610 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 1.634 ; 0.000         ;
; CLOCK_50                                           ; 2.558 ; 0.000         ;
+----------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                             ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 4.720   ; 0.000         ;
; CLOCK_50                                           ; 9.490   ; 0.000         ;
; altera_reserved_tck                                ; 49.495  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 49.738  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 249.743 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                      ; To Node                                                                                                                       ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 2.523 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.068     ; 7.404      ;
; 2.685 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.246      ;
; 2.693 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.238      ;
; 2.699 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[3]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.060     ; 2.236      ;
; 2.714 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.217      ;
; 2.716 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.215      ;
; 2.717 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.214      ;
; 2.717 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.214      ;
; 2.723 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.208      ;
; 2.727 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.204      ;
; 2.731 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.200      ;
; 2.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.190      ;
; 2.755 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[8]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.060     ; 2.180      ;
; 2.758 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[8]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.060     ; 2.177      ;
; 2.791 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[14]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[26]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.140      ;
; 2.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.096      ;
; 2.836 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.095      ;
; 2.839 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.092      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.851 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.070      ;
; 2.852 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.079      ;
; 2.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.052     ; 7.087      ;
; 2.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.052     ; 7.087      ;
; 2.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[6]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.052     ; 7.087      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 7.063      ;
; 2.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.073      ;
; 2.863 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.052     ; 7.080      ;
; 2.863 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.052     ; 7.080      ;
; 2.863 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[7]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.052     ; 7.080      ;
; 2.865 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[12]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.060     ; 2.070      ;
; 2.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.063     ; 7.057      ;
; 2.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.063     ; 7.057      ;
; 2.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.063     ; 7.057      ;
; 2.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.052      ;
; 2.887 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.044      ;
; 2.888 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.043      ;
; 2.889 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.042      ;
; 2.891 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.040      ;
; 2.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[16]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.057     ; 2.037      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 7.036      ;
; 2.902 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[15]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.061     ; 2.032      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.022      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.910 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.075     ; 7.010      ;
; 2.911 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.053     ; 7.031      ;
; 2.911 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.053     ; 7.031      ;
; 2.911 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[29]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.053     ; 7.031      ;
; 2.916 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_line_field[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.062     ; 7.017      ;
; 2.920 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[28]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.011      ;
; 2.921 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[15]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.061     ; 2.013      ;
; 2.926 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[14]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[22]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.005      ;
; 2.931 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[31]         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.064     ; 2.000      ;
; 2.931 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[0]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12]                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.060     ; 2.004      ;
; 2.937 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|full ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.071     ; 6.987      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[23]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[13] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[19]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.982      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[7]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[5]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[0]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[25]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[24]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[10]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
; 2.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_address_tag_field[12] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[8]                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.074     ; 6.981      ;
+-------+--------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                 ; To Node                                                                                                                                                                                                       ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 10.948 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 8.768      ;
; 11.041 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 8.675      ;
; 11.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 8.554      ;
; 11.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 8.511      ;
; 11.729 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 7.987      ;
; 11.787 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 7.929      ;
; 11.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 7.859      ;
; 11.931 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 7.785      ;
; 11.987 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 7.729      ;
; 12.293 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 7.647      ;
; 12.479 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.279     ; 7.237      ;
; 12.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|stop_cmd_r                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.366      ;
; 12.695 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|old_read                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.244      ;
; 12.752 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_valid       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 7.187      ;
; 12.756 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 7.215      ;
; 12.776 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.227      ;
; 12.849 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 7.122      ;
; 12.869 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.134      ;
; 12.876 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.127      ;
; 12.906 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.097      ;
; 12.969 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.034      ;
; 12.970 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 7.001      ;
; 12.990 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.013      ;
; 12.998 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 7.005      ;
; 13.013 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 6.958      ;
; 13.019 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.984      ;
; 13.033 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.970      ;
; 13.090 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.913      ;
; 13.111 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.892      ;
; 13.133 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.870      ;
; 13.140 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.863      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.558      ;
; 13.183 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.820      ;
; 13.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.771      ;
; 13.256 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.747      ;
; 13.257 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.274     ; 6.464      ;
; 13.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.728      ;
; 13.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 6.644      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.401      ;
; 13.417 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.274     ; 6.304      ;
; 13.419 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.584      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.444 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.280      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.483 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.271     ; 6.241      ;
; 13.532 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|last_channel[0]                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 6.407      ;
; 13.537 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 6.434      ;
; 13.538 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.274     ; 6.183      ;
; 13.541 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.462      ;
; 13.557 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.008      ; 6.446      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
; 13.564 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 6.323      ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                                                                ; To Node                                                                                                                                                                                                                                                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 47.558 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.243      ; 2.680      ;
; 47.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.243      ; 2.468      ;
; 47.793 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.243      ; 2.445      ;
; 47.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.242      ; 2.292      ;
; 47.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.248      ; 2.280      ;
; 47.988 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.243      ; 2.250      ;
; 48.251 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.243      ; 1.987      ;
; 48.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.246      ; 1.935      ;
; 48.330 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 1.918      ;
; 48.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.236      ; 1.898      ;
; 48.373 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.246      ; 1.868      ;
; 48.373 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.243      ; 1.865      ;
; 48.423 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.244      ; 1.816      ;
; 48.454 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.248      ; 1.789      ;
; 48.619 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.242      ; 1.618      ;
; 48.662 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.247      ; 1.580      ;
; 49.232 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.247      ; 1.010      ;
; 49.478 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.246      ; 0.763      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 95.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 3.948      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.867      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.860      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.135 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.086     ; 3.774      ;
; 96.144 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.782      ;
; 96.145 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.781      ;
; 96.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.758      ;
; 96.242 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.076     ; 3.677      ;
; 96.245 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.676      ;
; 96.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.675      ;
; 96.276 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.645      ;
; 96.304 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.622      ;
; 96.304 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.622      ;
; 96.305 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.621      ;
; 96.305 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.621      ;
; 96.309 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 3.617      ;
; 96.315 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.077     ; 3.603      ;
; 96.315 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.077     ; 3.603      ;
; 96.343 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.603      ;
; 96.343 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.603      ;
; 96.343 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.603      ;
; 96.343 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.603      ;
; 96.343 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.603      ;
; 96.387 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 3.526      ;
; 96.387 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 3.526      ;
; 96.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.518      ;
; 96.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.517      ;
; 96.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.516      ;
; 96.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.513      ;
; 96.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 3.512      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.087     ; 3.497      ;
; 96.429 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.076     ; 3.490      ;
; 96.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.513      ;
; 96.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.513      ;
; 96.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.513      ;
; 96.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.513      ;
; 96.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 3.513      ;
; 96.514 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 3.406      ;
; 96.515 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 3.405      ;
; 96.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 3.375      ;
; 96.554 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.084     ; 3.357      ;
; 96.571 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.052     ; 3.372      ;
; 96.571 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.052     ; 3.372      ;
; 96.575 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.076     ; 3.344      ;
; 96.592 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.076     ; 3.327      ;
; 96.635 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.076     ; 3.284      ;
; 96.644 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 3.297      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                    ; To Node                                                                                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 88.724 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.275     ; 10.996     ;
; 89.501 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.275     ; 10.219     ;
; 89.828 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 10.116     ;
; 90.090 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.045     ; 9.860      ;
; 90.252 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.275     ; 9.468      ;
; 90.438 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.275     ; 9.282      ;
; 90.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 9.435      ;
; 90.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.275     ; 9.174      ;
; 90.588 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.275     ; 9.132      ;
; 90.709 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.049     ; 9.262      ;
; 90.876 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[5]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.047     ; 9.072      ;
; 90.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 9.140      ;
; 91.005 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 9.029      ;
; 91.143 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 8.891      ;
; 91.302 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.052     ; 8.641      ;
; 91.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 8.694      ;
; 91.426 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[6]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.047     ; 8.522      ;
; 91.486 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.049     ; 8.485      ;
; 91.531 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 8.503      ;
; 91.588 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.045     ; 8.362      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.668 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 8.219      ;
; 91.671 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 8.363      ;
; 91.782 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 8.252      ;
; 91.805 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.061     ; 8.129      ;
; 91.813 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.175      ; 8.382      ;
; 91.814 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.047     ; 8.134      ;
; 91.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.061     ; 8.059      ;
; 91.891 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 8.143      ;
; 91.998 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.263      ; 8.260      ;
; 92.035 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.909      ;
; 92.075 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.181      ; 8.126      ;
; 92.088 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 7.946      ;
; 92.108 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.047     ; 7.840      ;
; 92.109 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.263      ; 8.149      ;
; 92.177 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[0]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.285     ; 7.533      ;
; 92.177 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[1]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.285     ; 7.533      ;
; 92.177 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[2]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.285     ; 7.533      ;
; 92.177 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[3]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.285     ; 7.533      ;
; 92.177 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[4]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.285     ; 7.533      ;
; 92.177 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.285     ; 7.533      ;
; 92.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.263      ; 8.037      ;
; 92.235 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.062     ; 7.698      ;
; 92.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.049     ; 7.734      ;
; 92.260 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.269      ; 8.004      ;
; 92.270 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.045     ; 7.680      ;
; 92.279 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 7.755      ;
; 92.292 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.052     ; 7.651      ;
; 92.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.062     ; 7.617      ;
; 92.348 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.307     ; 7.340      ;
; 92.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.269      ; 7.893      ;
; 92.376 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.568      ;
; 92.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.534      ;
; 92.418 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.263      ; 7.840      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 7.466      ;
; 92.422 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.039      ; 7.612      ;
; 92.423 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.049     ; 7.548      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                             ; To Node                                                                                                                                   ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 248.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.878      ;
; 248.053 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.861      ;
; 248.130 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.784      ;
; 248.288 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.626      ;
; 248.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.556      ;
; 248.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.554      ;
; 248.421 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.544      ;
; 248.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.346      ;
; 248.572 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.342      ;
; 248.694 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.072     ; 1.229      ;
; 248.695 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.219      ;
; 248.714 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.072     ; 1.209      ;
; 248.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.250      ;
; 248.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.113      ;
; 248.956 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.072     ; 0.967      ;
; 495.710 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 3.903      ;
; 495.976 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 3.964      ;
; 496.192 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 3.421      ;
; 496.469 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 3.144      ;
; 496.614 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.999      ;
; 496.614 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.999      ;
; 496.614 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.999      ;
; 496.704 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.909      ;
; 496.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.815      ;
; 496.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.815      ;
; 496.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.815      ;
; 496.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.815      ;
; 496.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.815      ;
; 496.801 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.815      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.829 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.787      ;
; 496.850 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 3.090      ;
; 496.880 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 3.060      ;
; 496.880 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 3.060      ;
; 496.880 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 3.060      ;
; 496.970 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.970      ;
; 497.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.928      ;
; 497.041 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.572      ;
; 497.061 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.868      ;
; 497.065 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.864      ;
; 497.066 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.863      ;
; 497.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.876      ;
; 497.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.876      ;
; 497.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.876      ;
; 497.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.876      ;
; 497.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.876      ;
; 497.067 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.876      ;
; 497.072 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.857      ;
; 497.074 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.855      ;
; 497.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.852      ;
; 497.078 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.851      ;
; 497.082 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.847      ;
; 497.086 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.843      ;
; 497.087 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.842      ;
; 497.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.836      ;
; 497.094 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.846      ;
; 497.094 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.846      ;
; 497.094 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.846      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 2.848      ;
; 497.095 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.834      ;
; 497.098 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.831      ;
; 497.099 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.830      ;
; 497.104 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.825      ;
; 497.125 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.804      ;
; 497.140 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.800      ;
; 497.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.454      ;
; 497.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.454      ;
; 497.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.454      ;
; 497.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.454      ;
; 497.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.454      ;
; 497.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.454      ;
; 497.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.446      ;
; 497.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.446      ;
; 497.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.446      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.379     ; 2.417      ;
; 497.269 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.382     ; 2.344      ;
; 497.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.664      ;
; 497.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.664      ;
; 497.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 2.664      ;
; 497.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.648      ;
; 497.285 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.644      ;
; 497.286 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.643      ;
; 497.292 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.066     ; 2.637      ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                                                                              ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[30]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.341      ; 0.742      ;
; 0.298 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[17]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.341      ; 0.808      ;
; 0.298 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mem_baddr[11]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.342      ; 0.809      ;
; 0.300 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mem_baddr[12]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.342      ; 0.811      ;
; 0.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[29]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.341      ; 0.815      ;
; 0.306 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[5]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.343      ; 0.818      ;
; 0.308 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.340      ; 0.817      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000100                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000100                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[0]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[0]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[2]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_count[2]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[0]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[0]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[2]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[2]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[2]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[2]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|empty                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|empty                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|full                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|full                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[1]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[1]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000100000                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000100000                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[15]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[15]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[9]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[9]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[13]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[13]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[12]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[12]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[11]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[11]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.340      ; 0.820      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|ac                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|ac                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[8]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[8]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[14]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[14]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[3]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[3]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|latched_oci_tb_hbreak_req                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|latched_oci_tb_hbreak_req                                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[48]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[48]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_fill_has_started                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_fill_has_started                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.000                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.000                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[0]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[0]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[1]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[1]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[2]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[2]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[0]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[0]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[1]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[1]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[2]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[2]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.000                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.000                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.101                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.101                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.101                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.101                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|init_done                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|init_done                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|rd_address                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|rd_address                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_rd                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_rd                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_has_started                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_has_started                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[1]                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[1]                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[2]                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[2]                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[1]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[1]                                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[2]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[2]                                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_active                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_active                                                                                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[80]                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[80]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][83]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][83]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|resetlatch                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|resetlatch                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|MonDReg[25]                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|MonDReg[25]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_ram_rd                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_ram_rd                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_next.010000000                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_next.010000000                                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|ack_refresh_request                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|ack_refresh_request                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|refresh_request                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|refresh_request                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000001                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_state.000000001                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|active_cs_n                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|active_cs_n                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[0]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[0]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|address_reg[1]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|address_reg[1]                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][55]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][55]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][57]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][57]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[80][101]                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[80][101]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[48][101]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[48][101]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[1]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[1]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][82]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][82]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[1]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[1]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[2]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[2]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[0]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[0]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[7]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[7]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][47]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][47]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][66]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][66]                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[10]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[10]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[4]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[4]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[2]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[2]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[1]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[1]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[5]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[5]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[0]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[0]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[6]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[6]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[80][65]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io2_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[80][65]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[48][65]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[48][65]                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[1]                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[1]                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[2]                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[2]                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_avalon_reg:the_DE0_Nano_SOPC_cpu_nios2_avalon_reg|oci_single_step_mode                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_avalon_reg:the_DE0_Nano_SOPC_cpu_nios2_avalon_reg|oci_single_step_mode                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|break_on_reset                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|break_on_reset                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|jtag_break                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|jtag_break                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ld_bypass_delayed_started                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ld_bypass_delayed_started                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_addr_cnt[1]                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_addr_cnt[1]                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_read                                                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_read                                                                                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_wr_active                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_wr_active                                                                                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                             ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.299 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.511      ;
; 0.299 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.511      ;
; 0.299 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.511      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.519      ;
; 0.329 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.541      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.538      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.539      ;
; 0.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.543      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.556      ;
; 0.360 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.559      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.560      ;
; 0.367 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.566      ;
; 0.367 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.566      ;
; 0.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.570      ;
; 0.451 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.650      ;
; 0.452 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.664      ;
; 0.464 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 0.666      ;
; 0.465 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.664      ;
; 0.466 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.665      ;
; 0.481 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.680      ;
; 0.499 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.698      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.699      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.699      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.699      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.698      ;
; 0.503 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.715      ;
; 0.510 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.708      ;
; 0.511 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.710      ;
; 0.515 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.714      ;
; 0.527 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.726      ;
; 0.528 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.727      ;
; 0.537 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.736      ;
; 0.537 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.736      ;
; 0.539 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.738      ;
; 0.541 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.740      ;
; 0.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.745      ;
; 0.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.744      ;
; 0.550 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.748      ;
; 0.550 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.748      ;
; 0.572 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.771      ;
; 0.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.777      ;
; 0.579 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.778      ;
; 0.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.779      ;
; 0.591 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.790      ;
; 0.595 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.794      ;
; 0.605 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.068      ; 0.817      ;
; 0.617 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.054      ; 0.815      ;
; 0.623 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.382      ; 1.149      ;
; 0.626 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.825      ;
; 0.627 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.826      ;
; 0.632 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.831      ;
; 0.652 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.382      ; 1.178      ;
; 0.655 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.854      ;
; 0.655 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.854      ;
; 0.657 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 0.856      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                  ; To Node                                                                                                                                                                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|pending_response_count[0]                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|pending_response_count[0]                                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_primed                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_primed                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|transmitting                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|transmitting                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|SCLK_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|SCLK_reg                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|MISO_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|MISO_reg                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_RW                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_RW                                                                                                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|s_readdata[0]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|s_readdata[0]                                                                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|pfdena_reg                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|pfdena_reg                                                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[1]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_scl:i2c_scl|data_out                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_scl:i2c_scl|data_out                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_dir                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_dir                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_out                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_out                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|slowcount[0]                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|slowcount[0]                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|state[4]                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|state[4]                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
; 0.321 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|wait_latency_counter[0]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|wait_latency_counter[0]                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.519      ;
; 0.321 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[0]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.519      ;
; 0.325 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 0.538      ;
; 0.325 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 0.538      ;
; 0.325 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 0.538      ;
; 0.326 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 0.539      ;
; 0.326 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 0.539      ;
; 0.326 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 0.539      ;
; 0.328 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 0.538      ;
; 0.329 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 0.539      ;
; 0.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_rd_strobe                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.530      ;
; 0.333 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.068      ; 0.545      ;
; 0.334 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.533      ;
; 0.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[7]                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|clk_cnt[7]                                                                                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.535      ;
; 0.337 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.536      ;
; 0.338 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe4a[0]                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe5a[0]                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.537      ;
; 0.338 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.537      ;
; 0.338 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.537      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[7]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[7]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[11]                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[11]                                                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[9]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[8]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[8]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[1]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[1]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[0]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[0]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.540      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                          ; To Node                                                                                                                                                                                                            ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_select_i2c_clk:select_i2c_clk|data_out                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_select_i2c_clk:select_i2c_clk|data_out                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.054      ; 0.511      ;
; 0.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.320 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.324 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 0.537      ;
; 0.325 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 0.538      ;
; 0.327 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 0.540      ;
; 0.327 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.069      ; 0.540      ;
; 0.330 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.529      ;
; 0.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.530      ;
; 0.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.530      ;
; 0.335 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.534      ;
; 0.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.535      ;
; 0.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.536      ;
; 0.337 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.537      ;
; 0.337 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.537      ;
; 0.337 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.536      ;
; 0.338 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.537      ;
; 0.338 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.537      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.539      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[31]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[15]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[20]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[4]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.538      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[10]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[27]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[11]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.540      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.540      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.540      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.540      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.540      ;
; 0.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.543      ;
; 0.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.543      ;
; 0.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.544      ;
; 0.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|readdata[0]                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.543      ;
; 0.345 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.545      ;
; 0.346 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.545      ;
; 0.348 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.547      ;
; 0.348 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.547      ;
; 0.353 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.552      ;
; 0.362 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.561      ;
; 0.366 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.565      ;
; 0.366 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.565      ;
; 0.367 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.566      ;
; 0.368 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.567      ;
; 0.369 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.568      ;
; 0.372 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.571      ;
; 0.374 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.055      ; 0.573      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.056      ; 0.575      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                                                                         ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.511      ;
; 0.312 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.511      ;
; 0.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 0.511      ;
; 0.319 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.519      ;
; 0.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.519      ;
; 0.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.519      ;
; 0.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.519      ;
; 0.325 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.538      ;
; 0.330 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.530      ;
; 0.330 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.530      ;
; 0.335 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.534      ;
; 0.336 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.536      ;
; 0.337 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.537      ;
; 0.338 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.538      ;
; 0.338 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.538      ;
; 0.338 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.538      ;
; 0.338 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.537      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.539      ;
; 0.339 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.539      ;
; 0.339 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.539      ;
; 0.339 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.539      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.539      ;
; 0.341 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.541      ;
; 0.341 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.540      ;
; 0.343 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.543      ;
; 0.345 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[37]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[36]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 0.557      ;
; 0.345 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.545      ;
; 0.345 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.544      ;
; 0.345 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.544      ;
; 0.345 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.545      ;
; 0.345 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.544      ;
; 0.346 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.545      ;
; 0.346 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.545      ;
; 0.347 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[0]                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.546      ;
; 0.347 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.546      ;
; 0.347 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.546      ;
; 0.347 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.546      ;
; 0.347 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.546      ;
; 0.348 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.547      ;
; 0.355 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.555      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.556      ;
; 0.356 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.556      ;
; 0.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.556      ;
; 0.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[14]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.556      ;
; 0.358 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.557      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.562      ;
; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.627      ;
; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.627      ;
; 0.431 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.631      ;
; 0.431 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.630      ;
; 0.432 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.632      ;
; 0.434 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.633      ;
; 0.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.649      ;
; 0.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[12]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.648      ;
; 0.451 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[11]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[10]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.650      ;
; 0.452 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[1]                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.665      ;
; 0.453 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.652      ;
; 0.454 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.654      ;
; 0.455 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.655      ;
; 0.464 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.664      ;
; 0.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.666      ;
; 0.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.666      ;
; 0.469 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.669      ;
; 0.470 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.669      ;
; 0.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.671      ;
; 0.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.671      ;
; 0.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.672      ;
; 0.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.673      ;
; 0.474 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.673      ;
; 0.475 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.675      ;
; 0.478 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.677      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.577 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.319      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[21]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.578 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.099     ; 2.318      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[26]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[10]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[6]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[22]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[18]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[2]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[14]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 2.580 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[30]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.106     ; 2.309      ;
; 7.105 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[8]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.158     ; 2.634      ;
; 7.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[10]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.157     ; 2.634      ;
; 7.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[13]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.157     ; 2.634      ;
; 7.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[9]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.157     ; 2.634      ;
; 7.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[11]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.157     ; 2.634      ;
; 7.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[14]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.157     ; 2.634      ;
; 7.118 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[2]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.160     ; 2.619      ;
; 7.119 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[12]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.161     ; 2.617      ;
; 7.119 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[7]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.160     ; 2.618      ;
; 7.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.206     ; 2.511      ;
; 7.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[0]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.206     ; 2.511      ;
; 7.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.083     ; 2.639      ;
; 7.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[2]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.083     ; 2.639      ;
; 7.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[3]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 2.638      ;
; 7.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[6]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 2.638      ;
; 7.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[8]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.083     ; 2.639      ;
; 7.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[9]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 2.639      ;
; 7.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[10]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 2.639      ;
; 7.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[11]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 2.639      ;
; 7.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[13]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 2.639      ;
; 7.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[14]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 2.639      ;
; 7.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_bank[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.083     ; 2.638      ;
; 7.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[4]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 2.627      ;
; 7.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[5]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.624      ;
; 7.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[2]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.624      ;
; 7.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[7]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.622      ;
; 7.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[7]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.623      ;
; 7.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[12]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.622      ;
; 7.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_bank[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 2.624      ;
; 7.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_dqm[0]                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.622      ;
; 7.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_dqm[1]                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.086     ; 2.622      ;
; 7.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.113     ; 2.596      ;
; 7.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.113     ; 2.596      ;
; 7.204 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[3]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.185     ; 2.508      ;
; 7.210 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[15]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.180     ; 2.507      ;
; 7.210 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[4]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.180     ; 2.507      ;
; 7.211 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[6]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.177     ; 2.509      ;
; 7.211 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[5]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.177     ; 2.509      ;
; 7.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.087     ; 2.600      ;
; 7.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[9]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.087     ; 2.600      ;
; 7.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[8]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.087     ; 2.599      ;
; 7.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[10]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.095     ; 2.591      ;
; 7.220 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[3]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.593      ;
; 7.220 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[11]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.092     ; 2.593      ;
; 7.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[12]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.089     ; 2.592      ;
; 7.226 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[4]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.087     ; 2.592      ;
; 7.226 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[15]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.087     ; 2.592      ;
; 7.227 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[5]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 2.594      ;
; 7.227 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[6]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.084     ; 2.594      ;
; 7.292 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.610      ;
; 7.292 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.610      ;
; 7.295 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.615      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[66]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[64]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[38]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[39]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.093     ; 2.606      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.614      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.614      ;
; 7.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.614      ;
; 7.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.597      ;
; 7.313 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.085     ; 2.597      ;
; 7.344 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_8                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.079     ; 2.459      ;
; 7.345 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_9                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.078     ; 2.459      ;
; 7.345 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_10                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.078     ; 2.459      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.331 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|read_latency_shift_reg[0]                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.060     ; 3.604      ;
; 16.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.603      ;
; 16.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.603      ;
; 16.336 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.603      ;
; 16.357 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.577      ;
; 16.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.575      ;
; 16.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.575      ;
; 16.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|CMD_START                                                                                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.569      ;
; 16.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_WRITE                                                                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.569      ;
; 16.371 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 3.569      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.516 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.168      ; 3.590      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|parity4                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[0]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.379      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[3]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 3.375      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[1]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[2]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.379      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|llreq                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[3]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 3.375      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[2]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.379      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[1]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[0]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.050     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[0]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[0]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[1]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[0]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[2]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[3]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[3]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[3]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.049     ; 3.378      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|parity5                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[3]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.043     ; 3.377      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.043     ; 3.377      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:wrptr_b|counter_reg_bit[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_wrusedw|dffe7a[1]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:wrptr_b|counter_reg_bit[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_ws_nbrp|dffe7a[2]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
; 16.575 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_wrusedw|dffe7a[2]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.044     ; 3.376      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.703 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.248      ; 1.540      ;
; 48.703 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0        ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.248      ; 1.540      ;
; 48.731 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.242      ; 1.506      ;
; 97.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.052     ; 2.013      ;
; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.796      ;
; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.796      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.171 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.770      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.761      ;
; 98.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.747      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.746      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.701      ;
; 98.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.540      ;
; 98.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.540      ;
; 98.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.540      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.523      ;
; 98.420 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 1.522      ;
; 98.420 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 1.522      ;
; 98.420 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 1.522      ;
; 98.420 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 1.522      ;
; 98.420 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 1.522      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.500      ;
; 98.827 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.113      ;
; 98.827 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.113      ;
; 98.827 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.113      ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                  ; To Node                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 97.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[1]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.072     ; 2.604      ;
; 97.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[3]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.072     ; 2.604      ;
; 97.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[2]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.072     ; 2.604      ;
; 97.319 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.072     ; 2.604      ;
; 97.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.067     ; 2.588      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.495 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.170      ; 2.613      ;
; 97.595 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.204      ; 2.604      ;
; 97.595 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.204      ; 2.604      ;
; 97.595 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.204      ; 2.604      ;
; 97.595 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.204      ; 2.604      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0]                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.085     ; 2.299      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.085     ; 2.299      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.085     ; 2.299      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.085     ; 2.299      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.085     ; 2.299      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.086     ; 2.298      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.085     ; 2.299      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[3]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.083     ; 2.301      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.611 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.082     ; 2.302      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.076     ; 2.299      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.077     ; 2.298      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[16]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[17]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[18]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[19]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[20]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[21]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[22]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[23]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[24]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[25]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[26]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[27]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[28]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[29]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[30]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_is_running                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.071     ; 2.304      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[31]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.074     ; 2.301      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[14]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.073     ; 2.302      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[30]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.073     ; 2.302      ;
; 97.620 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[14]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.073     ; 2.302      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 248.437 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.081     ; 1.477      ;
; 497.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.068     ; 2.024      ;
; 497.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.068     ; 2.024      ;
; 497.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.068     ; 2.024      ;
; 497.903 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.068     ; 2.024      ;
; 498.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.828      ;
; 498.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.828      ;
; 498.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.828      ;
; 498.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.828      ;
; 498.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.828      ;
; 498.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.828      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.756      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.051     ; 1.723      ;
; 498.397 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.046     ; 1.552      ;
; 498.397 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.046     ; 1.552      ;
; 498.397 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.046     ; 1.552      ;
; 498.397 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.046     ; 1.552      ;
; 498.397 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.046     ; 1.552      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.402 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.541      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.428 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.054     ; 1.513      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.446 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.052     ; 1.497      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.260      ;
; 498.757 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.259      ; 1.497      ;
; 498.757 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.259      ; 1.497      ;
; 498.757 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.259      ; 1.497      ;
; 498.757 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.259      ; 1.497      ;
; 498.790 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.150      ;
; 498.790 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.150      ;
; 498.790 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.150      ;
; 498.790 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.150      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
; 498.807 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.055     ; 1.133      ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.791  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.990      ;
; 0.791  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.990      ;
; 0.791  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 0.990      ;
; 1.191  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 1.393      ;
; 1.191  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 1.393      ;
; 1.191  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 1.393      ;
; 1.191  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 1.393      ;
; 1.191  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 1.393      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.195  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.396      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.199  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.398      ;
; 1.204  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.405      ;
; 1.204  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.405      ;
; 1.204  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.405      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.395  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 1.595      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.421  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.622      ;
; 1.432  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 1.630      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.449  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.057      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.456  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.650      ;
; 1.464  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 1.662      ;
; 1.464  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 1.662      ;
; 1.686  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.889      ;
; 50.866 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.355      ; 1.385      ;
; 50.882 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate         ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.359      ; 1.405      ;
; 50.882 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0        ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.359      ; 1.405      ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.822 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.021      ;
; 0.824 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.023      ;
; 0.824 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.023      ;
; 0.824 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.023      ;
; 0.824 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.023      ;
; 0.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.382      ; 1.401      ;
; 0.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.382      ; 1.401      ;
; 0.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.382      ; 1.401      ;
; 0.875 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.382      ; 1.401      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 0.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.154      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.401      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.212 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.411      ;
; 1.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.064      ; 1.426      ;
; 1.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.064      ; 1.426      ;
; 1.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.064      ; 1.426      ;
; 1.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.064      ; 1.426      ;
; 1.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.064      ; 1.426      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.232 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.434      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.409 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.059      ; 1.612      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.449 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.058      ; 1.651      ;
; 1.507 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.706      ;
; 1.507 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.706      ;
; 1.507 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.706      ;
; 1.507 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.706      ;
; 1.507 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.706      ;
; 1.507 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.055      ; 1.706      ;
; 1.665 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.069      ; 1.878      ;
; 1.665 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.069      ; 1.878      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.610 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.155      ;
; 1.610 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.155      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.618 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1]                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.401      ; 2.163      ;
; 1.619 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[1]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.400      ; 2.163      ;
; 1.619 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[2]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.400      ; 2.163      ;
; 1.619 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[4]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.400      ; 2.163      ;
; 1.619 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[5]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.400      ; 2.163      ;
; 1.621 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[2]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.391      ; 2.156      ;
; 1.621 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[3]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.391      ; 2.156      ;
; 1.621 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[4]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.391      ; 2.156      ;
; 1.621 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[0]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.391      ; 2.156      ;
; 1.621 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[1]                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.391      ; 2.156      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.377      ; 2.155      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.377      ; 2.155      ;
; 1.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.387      ; 2.168      ;
; 1.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.387      ; 2.168      ;
; 1.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq4                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.387      ; 2.168      ;
; 1.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq2                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.387      ; 2.168      ;
; 1.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq5                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.387      ; 2.168      ;
; 1.637 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq3                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.387      ; 2.168      ;
; 1.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[1]                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 2.167      ;
; 1.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[2]                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 2.167      ;
; 1.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[3]                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 2.167      ;
; 1.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[4]                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 2.167      ;
; 1.642 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[0]                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.381      ; 2.167      ;
; 1.645 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.370      ; 2.159      ;
; 1.645 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.370      ; 2.159      ;
; 1.645 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.370      ; 2.159      ;
; 1.645 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.370      ; 2.159      ;
; 1.645 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.370      ; 2.159      ;
; 1.645 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.370      ; 2.159      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_valid                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.365      ; 2.162      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[11]                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.365      ; 2.162      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[10]                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.365      ; 2.162      ;
; 1.654 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.362      ; 2.160      ;
; 1.654 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.362      ; 2.160      ;
; 1.654 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.362      ; 2.160      ;
; 1.654 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.362      ; 2.160      ;
; 1.952 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.344      ; 2.440      ;
; 1.952 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.344      ; 2.440      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ienable_reg_irq0                                                                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.059      ; 2.163      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_ctrl_late_result                                                                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.058      ; 2.162      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_ctrl_late_result                                                                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.059      ; 2.163      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_kill                                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.057      ; 2.161      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_iw_valid                                                                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.057      ; 2.161      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_extra_pc[0]                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.053      ; 2.157      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[1]                                                                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.053      ; 2.157      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_ctrl_jmp_indirect                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_pipe_flush_waddr[1]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.053      ; 2.157      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[2]                                                                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.053      ; 2.157      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_extra_pc[2]                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.053      ; 2.157      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_pipe_flush_waddr[2]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.053      ; 2.157      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[23]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.057      ; 2.161      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[15]                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.057      ; 2.161      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[22]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[1]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.062      ; 2.166      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.062      ; 2.166      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_actual_tag[17]                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.059      ; 2.163      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_tag[17]                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.059      ; 2.163      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[21]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.057      ; 2.161      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[21]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[14]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_avalon_reg:the_DE0_Nano_SOPC_cpu_nios2_avalon_reg|oci_ienable[20]                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|F_pc[8]                                                                                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.051      ; 2.155      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[0]                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.060      ; 2.164      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_sel_data_master                                                                                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.061      ; 2.165      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_offset[0]                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.061      ; 2.165      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_offset[1]                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.061      ; 2.165      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_offset[2]                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.061      ; 2.165      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|clr_break_line                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.057      ; 2.161      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|rvalid                                                                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.054      ; 2.158      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_readdata_pre[15]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.054      ; 2.158      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|read_latency_shift_reg[0]                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|endofpacket_reg                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.062      ; 2.166      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[15]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_pipe_flush_waddr[15]                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[4]                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.060      ; 2.164      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_writedata[2]                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.060      ; 2.164      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|fifo_wr                                                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.054      ; 2.158      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[19]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_pipe_flush_waddr[19]                                                                                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.049      ; 2.153      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|F_pc[19]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.061      ; 2.165      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_pc[12]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
; 1.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_pc[12]                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.055      ; 2.159      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                                                                            ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.385      ; 2.163      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.379      ; 2.157      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.379      ; 2.157      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.379      ; 2.157      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.379      ; 2.157      ;
; 1.634 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.379      ; 2.157      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[1]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[0]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.072      ; 2.162      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.054      ; 2.145      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[3]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.054      ; 2.145      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.054      ; 2.145      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.054      ; 2.145      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.063      ; 2.154      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.064      ; 2.155      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.054      ; 2.145      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[16]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[17]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[18]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[19]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[20]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[21]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[22]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[23]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[24]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[25]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[26]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[27]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[28]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[29]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[30]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_is_running                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[31]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.065      ; 2.156      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[14]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[30]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[14]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[13]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[29]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[13]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[13]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[12]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[12]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[10]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[10]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[10]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.066      ; 2.157      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[9]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[25]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[9]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[9]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[24]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[8]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[8]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[8]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[7]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[7]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[23]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[7]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[7]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[6]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[6]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[22]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[6]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[6]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[5]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.068      ; 2.159      ;
; 1.947 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[5]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.062      ; 2.153      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 2.558 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.409      ; 3.111      ;
; 2.558 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.409      ; 3.111      ;
; 2.566 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.411      ; 3.121      ;
; 2.566 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.411      ; 3.121      ;
; 2.566 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.411      ; 3.121      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[38]                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|prev_reset                                                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe6a[0]                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.401      ; 3.112      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[4]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.582 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.387      ; 3.113      ;
; 2.685 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|spi_clk                                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.288      ; 3.117      ;
; 2.896 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe4a[0]                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.105      ;
; 2.896 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe5a[0]                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[0]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[1]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[2]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[3]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[4]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[5]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[6]                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|full                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[9]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[0]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[1]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[2]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[3]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[2]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[4]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[5]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[1]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[0]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[6]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[7]                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[7]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.105      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[9]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[8]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[8]                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[8]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[7]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[6]                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[5]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[4]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.908 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[3]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.110      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1]  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.348      ; 3.401      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[31]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[26]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[25]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[24]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[19]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[16]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|wr_strobe                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 3.109      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_wr_strobe                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 3.109      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[15]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 3.111      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iEOP_reg                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 3.109      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[2]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.106      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[0]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.106      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[1]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.106      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[3]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.106      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[3]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 3.107      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 3.107      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 3.107      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[5]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.106      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[4]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.106      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[5]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 3.107      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[4]                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 3.107      ;
; 2.909 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 3.107      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+--------------+----------------+-----------------+----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                                                                                                                                                                              ;
+-------+--------------+----------------+-----------------+----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[0]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[10]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[11]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[12]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[13]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[14]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[15]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[16]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[17]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[18]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[19]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[1]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[20]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[21]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[22]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[23]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[24]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[25]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[26]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[27]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[28]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[29]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[2]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[30]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[31]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[3]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[4]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[5]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[6]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[7]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[8]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src1[9]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[0]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[0]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[10]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[10]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[11]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[11]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[12]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[12]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[13]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[13]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[14]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[14]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[15]                                                                                                                                                                                                                                                                               ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[15]~_Duplicate_1                                                                                                                                                                                                                                                                  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[1]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[1]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[2]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[2]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[3]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[3]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[4]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[4]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[5]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[5]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[6]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[6]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[7]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[7]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[8]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[8]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[9]                                                                                                                                                                                                                                                                                ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mul_src2[9]~_Duplicate_1                                                                                                                                                                                                                                                                   ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[0]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[10] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[11] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[12] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[13] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[14] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[15] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[16] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[17] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[18] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[19] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[1]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[20] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[21] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[22] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[23] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[24] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[25] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[26] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[27] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[28] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[29] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[2]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[30] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[31] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[3]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[4]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[5]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[6]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[7]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[8]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_1|altera_mult_add_q1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[9]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[0]  ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[10] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[11] ;
; 4.720 ; 4.991        ; 0.271          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_mult_cell:the_DE0_Nano_SOPC_cpu_mult_cell|altera_mult_add:the_altmult_add_part_2|altera_mult_add_s1u2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0|data_out_wire[12] ;
+-------+--------------+----------------+-----------------+----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                                                                                                                                                                                 ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                                                                                                                                                                             ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.490 ; 9.720        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|altsyncram:the_boot_copier_rom|altsyncram_u341:auto_generated|ram_block1a0~porta_address_reg0                                                             ;
; 9.490 ; 9.720        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_address_reg0      ;
; 9.490 ; 9.720        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_we_reg            ;
; 9.492 ; 9.722        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_datain_reg0       ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0      ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                          ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                           ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                           ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                           ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                           ;
; 9.499 ; 9.729        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                           ;
; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;
; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;
; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;
; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;
; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[4]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                             ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                     ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                     ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                    ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                     ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_rd_strobe                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[4]                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_wr_strobe                                                                                          ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[0]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[10]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[11]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[15]                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[1]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[2]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[3]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[4]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[5]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[6]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[7]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[8]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[9]                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[0]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[1]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[2]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[3]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[4]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[5]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[6]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[7]                                                                        ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iEOP_reg                                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iE_reg                                                                                                  ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iROE_reg                                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iRRDY_reg                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iTOE_reg                                                                                                ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iTRDY_reg                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                                                                                 ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                               ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[3]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[4]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[5]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[6]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[0]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[1]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[2]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[3]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[4]                                                                                       ;
; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[5]                                                                                       ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.495 ; 49.711       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ;
; 49.495 ; 49.711       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0                                                                                                                                                                                                                         ;
; 49.497 ; 49.713       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                                                                               ;
; 49.532 ; 49.716       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ;
; 49.532 ; 49.716       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ;
; 49.532 ; 49.716       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[1]                                                    ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ;
; 49.535 ; 49.719       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.000                                                   ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.010                                                   ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.100                                                   ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[0]                                                    ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[10]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[11]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[12]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[14]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[15]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[1]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[2]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[33]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[34]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[35]                                                       ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[3]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[4]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[5]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[6]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[8]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[9]                                                        ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                                                                                                                                                           ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                                                                                                                                                                  ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                  ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ;
; 49.536 ; 49.720       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                                                                                ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav                                                                                                                                                                                                                        ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]                                                                                                                                                                                                                         ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid                                                                                                                                                                                                                      ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                                                                                ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                                                                              ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ;
; 49.537 ; 49.721       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.738 ; 49.954       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                                                                                                   ;
; 49.738 ; 49.954       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                                                                                                   ;
; 49.738 ; 49.954       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                                                                                                   ;
; 49.738 ; 49.954       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                                                                                                   ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[0]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[10]                                                                                                                                    ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[11]                                                                                                                                    ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[12]                                                                                                                                    ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[13]                                                                                                                                    ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[14]                                                                                                                                    ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[15]                                                                                                                                    ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[1]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[2]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[3]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[4]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[5]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[6]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[7]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[8]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[9]                                                                                                                                     ;
; 49.743 ; 49.959       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[0]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[0]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[1]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[2]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[3]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[4]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[5]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[6]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_led:led|data_out[7]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[3]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                                                                                                 ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[0]                                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[2]                                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[3]                                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[0]                                                                                                                                     ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[15]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[16]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[17]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[18]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[19]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[1]                                                                                                                                     ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[21]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[2]                                                                                                                                     ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[3]                                                                                                                                     ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[0]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[10]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[11]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[12]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[13]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[14]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[15]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[2]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[3]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[5]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[7]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[8]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_h_register[9]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[0]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[10]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[11]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[12]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[13]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[14]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[15]                                                                                                                                   ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[1]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[2]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[3]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[4]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[5]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[6]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[7]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[8]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|period_l_register[9]                                                                                                                                    ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[0]                                                                                                                                             ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[2]                                                                                                                                             ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[3]                                                                                                                                             ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;
; 49.744 ; 49.960       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                       ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ;
; 249.743 ; 249.959      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                                                             ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                                                             ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                                                             ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                         ;
; 249.744 ; 249.960      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                        ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                     ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                     ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ;
; 249.745 ; 249.961      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                 ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; 1.520 ; 1.949 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 1.645 ; 2.104 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; 0.955 ; 1.200 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 0.955 ; 1.200 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 0.955 ; 1.200 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 0.922 ; 1.169 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 0.948 ; 1.193 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 0.943 ; 1.188 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 0.940 ; 1.185 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 0.940 ; 1.185 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 0.922 ; 1.169 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 0.920 ; 1.167 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 0.919 ; 1.166 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 0.919 ; 1.166 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 0.919 ; 1.166 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 0.923 ; 1.170 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 0.919 ; 1.166 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 0.919 ; 1.166 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 0.943 ; 1.188 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; 2.513 ; 2.732 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; 3.959 ; 4.437 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; 3.959 ; 4.437 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; 2.377 ; 2.667 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; 2.824 ; 3.071 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; 2.580 ; 2.865 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; 2.604 ; 2.802 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; 2.824 ; 3.071 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; 2.559 ; 2.867 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; 1.780 ; 2.031 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; 2.968 ; 3.270 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; 7.359 ; 7.540 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; -1.183 ; -1.595 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; -1.263 ; -1.689 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; -0.449 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; -0.483 ; -0.728 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; -0.483 ; -0.728 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; -0.452 ; -0.699 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; -0.475 ; -0.720 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; -0.470 ; -0.715 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; -0.466 ; -0.711 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; -0.466 ; -0.711 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; -0.453 ; -0.700 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; -0.450 ; -0.697 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; -0.450 ; -0.697 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; -0.449 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; -0.449 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; -0.453 ; -0.700 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; -0.449 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; -0.449 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; -0.470 ; -0.715 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; -1.679 ; -1.855 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; -1.185 ; -1.424 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; -2.935 ; -3.385 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; -1.185 ; -1.424 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; -1.366 ; -1.617 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; -1.388 ; -1.620 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; -1.641 ; -1.819 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; -1.619 ; -1.813 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; -1.366 ; -1.617 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; -1.049 ; -1.264 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; -0.173 ; -0.415 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; -2.156 ; -2.362 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                         ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 6.118  ; 6.083  ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 5.233  ; 5.254  ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 7.162  ; 7.072  ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 8.279  ; 8.101  ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 6.748  ; 6.595  ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 2.644  ; 2.550  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 2.644  ; 2.550  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 2.568  ; 2.493  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 2.568  ; 2.493  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 2.567  ; 2.492  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 2.570  ; 2.495  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 2.566  ; 2.491  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 2.567  ; 2.492  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 2.565  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 2.562  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 2.644  ; 2.550  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 2.636  ; 2.542  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 2.639  ; 2.545  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 2.559  ; 2.487  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 2.568  ; 2.493  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 2.566  ; 2.491  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 2.568  ; 2.493  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 2.645  ; 2.551  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 4.334  ; 3.921  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 2.648  ; 2.554  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 2.631  ; 2.537  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 2.631  ; 2.537  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 2.566  ; 2.491  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 2.556  ; 2.484  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 2.644  ; 2.550  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 2.648  ; 2.554  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 2.648  ; 2.554  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 2.565  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 2.568  ; 2.493  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 2.568  ; 2.493  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 2.569  ; 2.494  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 2.569  ; 2.494  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 2.565  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 2.569  ; 2.494  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 2.569  ; 2.494  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 2.644  ; 2.550  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 2.565  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 2.565  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 2.565  ; 2.490  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 2.645  ; 2.551  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 2.641  ; 2.547  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; 0.648  ;        ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;        ; 0.539  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 5.897  ; 5.762  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 6.969  ; 6.651  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 4.220  ; 4.136  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 4.701  ; 4.629  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 4.945  ; 4.869  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 3.922  ; 3.834  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 4.768  ; 4.792  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 6.969  ; 6.651  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 4.868  ; 4.791  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 6.272  ; 5.872  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 4.326  ; 4.204  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 4.851  ; 4.635  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 4.147  ; 4.051  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;        ; 3.762  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 10.898 ; 11.269 ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                               ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 5.912 ; 5.876 ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 5.041 ; 5.061 ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 6.131 ; 6.057 ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 6.468 ; 6.280 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 6.282 ; 6.112 ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 2.203 ; 2.131 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 2.288 ; 2.194 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 2.214 ; 2.138 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 2.214 ; 2.138 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 2.213 ; 2.137 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 2.215 ; 2.139 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 2.212 ; 2.136 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 2.213 ; 2.137 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 2.211 ; 2.135 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 2.205 ; 2.133 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 2.288 ; 2.194 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 2.280 ; 2.186 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 2.283 ; 2.189 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 2.203 ; 2.131 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 2.213 ; 2.137 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 2.213 ; 2.137 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 2.214 ; 2.138 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 2.288 ; 2.194 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 3.981 ; 3.567 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 2.200 ; 2.128 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 2.276 ; 2.182 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 2.276 ; 2.182 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 2.212 ; 2.136 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 2.200 ; 2.128 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 2.288 ; 2.194 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 2.291 ; 2.197 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 2.291 ; 2.197 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 2.212 ; 2.136 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 2.214 ; 2.138 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 2.215 ; 2.139 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 2.215 ; 2.139 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 2.215 ; 2.139 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 2.211 ; 2.135 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 2.215 ; 2.139 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 2.215 ; 2.139 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 2.288 ; 2.194 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 2.211 ; 2.135 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 2.211 ; 2.135 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 2.211 ; 2.135 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 2.288 ; 2.194 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 2.285 ; 2.191 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; 0.237 ;       ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;       ; 0.129 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 5.319 ; 5.156 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 3.439 ; 3.351 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 3.725 ; 3.642 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 4.187 ; 4.115 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 4.421 ; 4.345 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 3.439 ; 3.351 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 4.253 ; 4.272 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 6.434 ; 6.111 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 4.345 ; 4.269 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 5.765 ; 5.363 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 3.690 ; 3.668 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 3.463 ; 4.092 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 3.655 ; 3.559 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;       ; 3.291 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 8.653 ; 9.028 ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                         ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 6.137 ; 5.995 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.398 ; 2.275 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.477 ; 2.335 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.477 ; 2.335 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.401 ; 2.276 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.398 ; 2.287 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.490 ; 2.348 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.494 ; 2.352 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.494 ; 2.352 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.400 ; 2.275 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.403 ; 2.278 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.403 ; 2.278 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.404 ; 2.279 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.404 ; 2.279 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.400 ; 2.275 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.404 ; 2.279 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.404 ; 2.279 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.490 ; 2.348 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                 ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 5.874 ; 5.732 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.044 ; 1.923 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.124 ; 1.982 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.124 ; 1.982 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.049 ; 1.924 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.044 ; 1.933 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.136 ; 1.994 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.139 ; 1.997 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.139 ; 1.997 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.049 ; 1.924 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.051 ; 1.926 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.052 ; 1.927 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.052 ; 1.927 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.052 ; 1.927 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.048 ; 1.923 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.052 ; 1.927 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.052 ; 1.927 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.136 ; 1.994 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 6.020     ; 6.162     ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 2.306     ; 2.431     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.390     ; 2.532     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.390     ; 2.532     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 2.307     ; 2.432     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 2.342     ; 2.453     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.403     ; 2.545     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.407     ; 2.549     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.407     ; 2.549     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 2.306     ; 2.431     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 2.309     ; 2.434     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 2.309     ; 2.434     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 2.310     ; 2.435     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 2.310     ; 2.435     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 2.306     ; 2.431     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 2.310     ; 2.435     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 2.310     ; 2.435     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.403     ; 2.545     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                        ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 5.737     ; 5.879     ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 1.953     ; 2.078     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 2.035     ; 2.177     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 2.035     ; 2.177     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 1.954     ; 2.079     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 1.986     ; 2.097     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 2.047     ; 2.189     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 2.050     ; 2.192     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 2.050     ; 2.192     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 1.954     ; 2.079     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 1.956     ; 2.081     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 1.957     ; 2.082     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 1.957     ; 2.082     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 1.957     ; 2.082     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 1.953     ; 2.078     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 1.957     ; 2.082     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 1.957     ; 2.082     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 2.047     ; 2.189     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+


----------------
; MTBF Summary ;
----------------
Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.

Number of Synchronizer Chains Found: 64
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
Worst Case Available Settling Time: 15.302 ns

Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+
; Source Node                                                                                                                                                                                              ; Synchronization Node                                                                                                                                                                                                                                                                                                                                                 ; Typical MTBF (Years)   ; Included in Design MTBF ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
;                                                                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                ; Greater than 1 Billion ; Yes                     ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ; Greater than 1 Billion ; Yes                     ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                              ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1       ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1       ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+


Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 15.302                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                              ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 9.007        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 6.295        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 15.409                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 0.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 9.008        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 6.401        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                       ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                       ; 15.664                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                          ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                          ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 9.059        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 6.605        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 15.971                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 0.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 9.073        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 6.898        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #5: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                   ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                 ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ;                                                                                                                                                                                                                                                       ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                   ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                   ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                            ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                            ; 18.637                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                               ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                     ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                   ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                     ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1  ;                        ;              ;                  ; 9.328        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ;                        ;              ;                  ; 9.309        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #6: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                    ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                           ; 18.647                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                              ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                                   ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                      ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1  ;                        ;              ;                  ; 9.329        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ;                        ;              ;                  ; 9.318        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #7: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                    ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                           ; 18.651                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                              ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                                   ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                      ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1  ;                        ;              ;                  ; 9.330        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ;                        ;              ;                  ; 9.321        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #8: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.687                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.318        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.318        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 7.051        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #9: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 25.732                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.005        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.332        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 7.395        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #10: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 25.819                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.316        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.179        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 7.324        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #11: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.862                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 9.330        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 9.332        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 7.200        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #12: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 25.870                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;                        ;              ;                  ; 9.329        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;                        ;              ;                  ; 9.332        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|dreg[1] ;                        ;              ;                  ; 7.209        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #13: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.003                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.319        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.320        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.364        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #14: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 26.047                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.331        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.190        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.526        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #15: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 26.213                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.317        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.319        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 7.577        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #16: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.221                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 9.314        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 9.178        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 7.729        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #17: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 26.227                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.005        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.191        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 8.031        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #18: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 26.371                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.318        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.180        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 7.873        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #19: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.459                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 8.984        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.192        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 8.283        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #20: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.489                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.317        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.180        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 7.992        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #21: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 26.678                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.318        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.179        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.181        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #22: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                     ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                   ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                             ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                                                     ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                     ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                              ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                              ; 26.743                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                 ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                       ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                       ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.317        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.317        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.109        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #23: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 26.750                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.002        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.190        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.558        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #24: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.754                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.317        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.180        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.257        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #25: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.800                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.318        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.176        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 8.306        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #26: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                           ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 26.903                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|edge_capture                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.330        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.332        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.241        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #27: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 26.979                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 8.983        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.190        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.806        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #28: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 27.070                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.003        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.333        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.734        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #29: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.241                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 8.978        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.190        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.073        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #30: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.256                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 8.983        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.194        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 9.079        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #31: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 27.279                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.002        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.193        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 9.084        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #32: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.306                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.319        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.318        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.669        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #33: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 27.311                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.319        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.314        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.678        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #34: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 27.627                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[0]                                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.329        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.329        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.969        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #35: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 27.742                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                     ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.316        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.319        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.107        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #36: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 36.809                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                              ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 19.193       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 17.616       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #37: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                       ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                       ; 37.066                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                          ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 19.318       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 17.748       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #38: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 54.797                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 19.318       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 18.980       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 16.499       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #39: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 54.918                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 19.315       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 18.980       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 16.623       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #40: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 55.081                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 18.980       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 19.190       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 16.911       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #41: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 55.135                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;                        ;              ;                  ; 19.318       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;                        ;              ;                  ; 18.978       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[1] ;                        ;              ;                  ; 16.839       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #42: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 55.854                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 19.315       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 18.979       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 17.560       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #43: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 56.056                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 18.980       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 19.194       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 17.882       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #44: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 56.093                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 19.316       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 18.978       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 17.799       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #45: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 56.150                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 19.320       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 19.182       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 17.648       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #46: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 56.201                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 19.332       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 19.329       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 17.540       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #47: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 56.459                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 19.319       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 19.180       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 17.960       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #48: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.590                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 19.331       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 19.189       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 19.070       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #49: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.741                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 19.330       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 19.330       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 19.081       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #50: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                          ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                                                                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                         ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                         ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                            ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                             ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                     ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                     ; 197.360                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                        ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                              ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                             ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ;                        ;              ;                  ; 99.318       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ;                        ;              ;                  ; 98.042       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #51: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                          ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready                                                                                                                                                       ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                         ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                         ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                            ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                             ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                     ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                     ; 198.236                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                        ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                              ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                             ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ;                        ;              ;                  ; 99.329       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ;                        ;              ;                  ; 98.907       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #52: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 295.258                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 99.004       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 99.328       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 96.926       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #53: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 295.278                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 99.000       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 99.333       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 96.945       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #54: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 295.443                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 99.003       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 99.191       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 97.249       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #55: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 295.510                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 99.003       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 99.329       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 97.178       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #56: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 295.791                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 99.006       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 99.328       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 97.457       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #57: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 295.819                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 99.318       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 99.180       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 97.321       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #58: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 296.107                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 99.001       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 99.327       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 97.779       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #59: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 296.298                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 99.005       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 99.192       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 98.101       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #60: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.072                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 99.332       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 99.194       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 98.546       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #61: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.356                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 99.333       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 99.192       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 98.831       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #62: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.979                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 99.330       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 99.329       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 99.320       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #63: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 995.649                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 499.180      ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 496.469      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #64: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 996.741                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 499.192      ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 497.549      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



+------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                           ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 3.515   ; 0.000         ;
; CLOCK_50                                           ; 14.343  ; 0.000         ;
; altera_reserved_tck                                ; 48.712  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 92.677  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 248.755 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+----------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                          ;
+----------------------------------------------------+-------+---------------+
; Clock                                              ; Slack ; End Point TNS ;
+----------------------------------------------------+-------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.106 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.179 ; 0.000         ;
; CLOCK_50                                           ; 0.185 ; 0.000         ;
; altera_reserved_tck                                ; 0.186 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.187 ; 0.000         ;
+----------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                        ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 3.403   ; 0.000         ;
; CLOCK_50                                           ; 17.509  ; 0.000         ;
; altera_reserved_tck                                ; 49.433  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 98.210  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 248.993 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+----------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                       ;
+----------------------------------------------------+-------+---------------+
; Clock                                              ; Slack ; End Point TNS ;
+----------------------------------------------------+-------+---------------+
; altera_reserved_tck                                ; 0.495 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.500 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 1.070 ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 1.079 ; 0.000         ;
; CLOCK_50                                           ; 1.646 ; 0.000         ;
+----------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                             ;
+----------------------------------------------------+---------+---------------+
; Clock                                              ; Slack   ; End Point TNS ;
+----------------------------------------------------+---------+---------------+
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 4.749   ; 0.000         ;
; CLOCK_50                                           ; 9.209   ; 0.000         ;
; altera_reserved_tck                                ; 49.315  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 49.751  ; 0.000         ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 249.776 ; 0.000         ;
+----------------------------------------------------+---------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                             ;
+-------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                               ; To Node                                                                 ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 3.515 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[3]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.461      ;
; 3.542 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.431      ;
; 3.545 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.428      ;
; 3.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[8]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.430      ;
; 3.547 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.426      ;
; 3.547 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.426      ;
; 3.552 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[8]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.424      ;
; 3.552 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.421      ;
; 3.552 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.421      ;
; 3.563 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.410      ;
; 3.563 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.410      ;
; 3.565 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.408      ;
; 3.567 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.406      ;
; 3.610 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[14]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[26] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.362      ;
; 3.625 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.348      ;
; 3.626 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.347      ;
; 3.626 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.347      ;
; 3.632 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[12]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.344      ;
; 3.636 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.337      ;
; 3.638 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.335      ;
; 3.652 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.320      ;
; 3.656 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[16]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.009     ; 1.322      ;
; 3.659 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[25]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.052     ; 1.276      ;
; 3.659 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[15]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.316      ;
; 3.660 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.313      ;
; 3.671 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[15]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.304      ;
; 3.671 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[28]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.302      ;
; 3.673 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[31]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.300      ;
; 3.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[0]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.302      ;
; 3.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[9]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.052     ; 1.260      ;
; 3.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.297      ;
; 3.678 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.294      ;
; 3.678 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.294      ;
; 3.678 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[12]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.298      ;
; 3.679 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.293      ;
; 3.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[31]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.282      ;
; 3.696 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[5]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.279      ;
; 3.701 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[4]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.275      ;
; 3.702 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[17]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.013     ; 1.272      ;
; 3.703 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[14]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[22] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.269      ;
; 3.706 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[13]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.010     ; 1.271      ;
; 3.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[3]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.261      ;
; 3.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[27]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.258      ;
; 3.716 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[27]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.257      ;
; 3.719 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[5]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.256      ;
; 3.734 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[28]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.239      ;
; 3.735 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[21] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.237      ;
; 3.739 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.233      ;
; 3.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.225      ;
; 3.747 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[29]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.225      ;
; 3.771 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[18] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.196      ;
; 3.773 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[11]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.203      ;
; 3.775 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[26] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.192      ;
; 3.776 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[9]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[21] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.199      ;
; 3.777 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[0]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.199      ;
; 3.778 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.189      ;
; 3.782 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.185      ;
; 3.785 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[8]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.191      ;
; 3.786 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[13]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[21] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.010     ; 1.191      ;
; 3.788 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[4]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.188      ;
; 3.790 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[8]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.186      ;
; 3.813 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[29]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.159      ;
; 3.827 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[25]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.052     ; 1.108      ;
; 3.830 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[9]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.052     ; 1.105      ;
; 3.832 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[7]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.144      ;
; 3.842 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[21]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.130      ;
; 3.844 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[11]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.132      ;
; 3.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[23]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.127      ;
; 3.847 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[22]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.120      ;
; 3.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[23]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.119      ;
; 3.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[30] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.112      ;
; 3.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.111      ;
; 3.856 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[22] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.111      ;
; 3.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[1]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.118      ;
; 3.857 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[17]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.013     ; 1.117      ;
; 3.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[9]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.117      ;
; 3.861 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[3]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.115      ;
; 3.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_rn[2]      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[14] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.105      ;
; 3.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[29]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.058     ; 1.059      ;
; 3.870 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[13]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.058     ; 1.059      ;
; 3.871 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[12]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.105      ;
; 3.872 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[25]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.100      ;
; 3.874 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[30]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.093      ;
; 3.876 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[24]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.097      ;
; 3.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[19]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.094      ;
; 3.880 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[19]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.093      ;
; 3.916 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[21]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.056      ;
; 3.921 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[20]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.052      ;
; 3.921 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[16]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.009     ; 1.057      ;
; 3.928 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[14]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[18] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.044      ;
; 3.933 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[1]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.012     ; 1.042      ;
; 3.938 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[7]   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.011     ; 1.038      ;
; 3.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[14]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[14] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.033      ;
; 3.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[22]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[30] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.028      ;
; 3.940 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[24]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.050     ; 0.997      ;
; 3.942 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[20]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.031      ;
; 3.949 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[25]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.015     ; 1.023      ;
; 3.953 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[24]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.014     ; 1.020      ;
; 3.955 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_rot[8]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.050     ; 0.982      ;
; 3.960 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_rot_step1[30]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.020     ; 1.007      ;
+-------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                 ; To Node                                                                                                                                                                                                       ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 14.343 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 5.463      ;
; 14.473 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 5.333      ;
; 14.553 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 5.253      ;
; 14.568 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 5.238      ;
; 14.858 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 4.948      ;
; 14.864 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 4.942      ;
; 14.972 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 4.834      ;
; 14.974 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 4.832      ;
; 15.029 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 4.777      ;
; 15.247 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 4.704      ;
; 15.297 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.181     ; 4.509      ;
; 15.443 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 4.532      ;
; 15.475 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.505      ;
; 15.487 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|stop_cmd_r                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 4.463      ;
; 15.499 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|old_read                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 4.451      ;
; 15.525 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_valid       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 4.425      ;
; 15.547 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.433      ;
; 15.551 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 4.424      ;
; 15.552 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.428      ;
; 15.605 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.375      ;
; 15.617 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.363      ;
; 15.625 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.355      ;
; 15.631 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 4.344      ;
; 15.646 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 4.329      ;
; 15.682 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.298      ;
; 15.685 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.295      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.120      ;
; 15.695 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.285      ;
; 15.697 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.283      ;
; 15.700 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.280      ;
; 15.712 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.268      ;
; 15.762 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.218      ;
; 15.775 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.205      ;
; 15.777 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.203      ;
; 15.790 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.190      ;
; 15.793 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.178     ; 4.016      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.799 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 4.012      ;
; 15.800 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.178     ; 4.009      ;
; 15.825 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.155      ;
; 15.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.134      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.879 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.932      ;
; 15.880 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.178     ; 3.929      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.176     ; 3.917      ;
; 15.895 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.178     ; 3.914      ;
; 15.926 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.054      ;
; 15.936 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 4.039      ;
; 15.939 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 4.012      ;
; 15.941 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.007     ; 4.039      ;
; 15.942 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 4.033      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
; 15.964 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 3.957      ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                                                                ; To Node                                                                                                                                                                                                                                                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.710      ;
; 48.828 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.594      ;
; 48.885 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.537      ;
; 48.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.440      ; 1.464      ;
; 48.979 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.443      ;
; 48.999 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.423      ;
; 49.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.249      ;
; 49.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.427      ; 1.234      ;
; 49.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.443      ; 1.230      ;
; 49.220 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.205      ;
; 49.245 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.177      ;
; 49.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.178      ;
; 49.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.147      ;
; 49.287 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 1.136      ;
; 49.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.017      ;
; 49.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.002      ;
; 49.776 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 0.649      ;
; 49.944 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 0.479      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.053     ; 2.507      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 2.490      ;
; 97.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 2.489      ;
; 97.467 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.476      ;
; 97.467 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.476      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.472 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.457      ;
; 97.485 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.458      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.420      ;
; 97.544 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 2.393      ;
; 97.544 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 2.393      ;
; 97.566 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.377      ;
; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.371      ;
; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.376      ;
; 97.568 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.370      ;
; 97.569 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.374      ;
; 97.570 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.373      ;
; 97.572 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.371      ;
; 97.593 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.345      ;
; 97.618 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.340      ;
; 97.618 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.340      ;
; 97.618 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.340      ;
; 97.618 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.340      ;
; 97.618 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.340      ;
; 97.647 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 2.290      ;
; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 2.256      ;
; 97.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.275      ;
; 97.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.275      ;
; 97.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.275      ;
; 97.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.275      ;
; 97.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.029     ; 2.275      ;
; 97.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.255      ;
; 97.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.254      ;
; 97.687 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.251      ;
; 97.687 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.251      ;
; 97.689 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.249      ;
; 97.692 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 2.239      ;
; 97.694 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 2.243      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 2.223      ;
; 97.730 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 2.202      ;
; 97.730 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 2.202      ;
; 97.764 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.174      ;
; 97.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.173      ;
; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 2.148      ;
; 97.840 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.103      ;
; 97.840 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.044     ; 2.103      ;
; 97.850 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 2.103      ;
; 97.850 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 2.103      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                    ; To Node                                                                                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 92.677 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.177     ; 7.133      ;
; 93.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.177     ; 6.615      ;
; 93.422 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 6.531      ;
; 93.660 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.028     ; 6.299      ;
; 93.672 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.177     ; 6.138      ;
; 93.806 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.177     ; 6.004      ;
; 93.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.035     ; 6.058      ;
; 93.941 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 6.034      ;
; 93.992 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.177     ; 5.818      ;
; 94.027 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.177     ; 5.783      ;
; 94.071 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.929      ;
; 94.111 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[5]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.029     ; 5.847      ;
; 94.148 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.852      ;
; 94.149 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.851      ;
; 94.266 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.734      ;
; 94.383 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.617      ;
; 94.459 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.516      ;
; 94.462 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.036     ; 5.489      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.494 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.427      ;
; 94.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[6]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.029     ; 5.449      ;
; 94.589 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.411      ;
; 94.666 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.028     ; 5.293      ;
; 94.666 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.334      ;
; 94.667 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.333      ;
; 94.686 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.109      ; 5.432      ;
; 94.782 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.042     ; 5.163      ;
; 94.784 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.216      ;
; 94.816 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.156      ; 5.327      ;
; 94.826 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.029     ; 5.132      ;
; 94.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[0]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.184     ; 4.949      ;
; 94.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[1]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.184     ; 4.949      ;
; 94.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[2]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.184     ; 4.949      ;
; 94.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[3]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.184     ; 4.949      ;
; 94.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[4]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.184     ; 4.949      ;
; 94.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.184     ; 4.949      ;
; 94.893 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.156      ; 5.250      ;
; 94.894 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.156      ; 5.249      ;
; 94.896 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.042     ; 5.049      ;
; 94.901 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 5.099      ;
; 94.924 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.115      ; 5.200      ;
; 94.936 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 5.039      ;
; 94.982 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.200     ; 4.805      ;
; 94.985 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.968      ;
; 95.011 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.156      ; 5.132      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.012 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.909      ;
; 95.054 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.162      ; 5.095      ;
; 95.066 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.013      ; 4.934      ;
; 95.070 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.034     ; 4.905      ;
; 95.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.029     ; 4.879      ;
; 95.094 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.199     ; 4.694      ;
; 95.105 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.042     ; 4.840      ;
; 95.111 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.199     ; 4.677      ;
; 95.124 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.035     ; 4.828      ;
; 95.128 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.156      ; 5.015      ;
; 95.131 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.162      ; 5.018      ;
; 95.132 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|stop_cmd_r                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.162      ; 5.017      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                                             ; To Node                                                                                                                                   ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 248.755 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.202      ;
; 248.769 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.188      ;
; 248.800 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.157      ;
; 248.927 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 1.030      ;
; 248.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 0.995      ;
; 248.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 0.995      ;
; 248.948 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 0.993      ;
; 249.072 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 0.885      ;
; 249.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 0.880      ;
; 249.131 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.046     ; 0.810      ;
; 249.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 0.796      ;
; 249.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.022     ; 0.765      ;
; 249.206 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.022     ; 0.759      ;
; 249.227 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 0.730      ;
; 249.369 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.022     ; 0.596      ;
; 497.324 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 2.429      ;
; 497.478 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 2.473      ;
; 497.597 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 2.156      ;
; 497.772 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.981      ;
; 497.937 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.816      ;
; 497.937 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.816      ;
; 497.937 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.816      ;
; 497.996 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.757      ;
; 498.004 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.947      ;
; 498.016 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.739      ;
; 498.016 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.739      ;
; 498.016 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.739      ;
; 498.016 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.739      ;
; 498.016 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.739      ;
; 498.016 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.739      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.036 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.719      ;
; 498.070 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.881      ;
; 498.082 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.869      ;
; 498.082 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.869      ;
; 498.082 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.869      ;
; 498.127 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.626      ;
; 498.139 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.801      ;
; 498.141 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.799      ;
; 498.142 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.798      ;
; 498.146 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.794      ;
; 498.147 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.793      ;
; 498.149 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.791      ;
; 498.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.801      ;
; 498.151 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.789      ;
; 498.153 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.787      ;
; 498.155 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.785      ;
; 498.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.784      ;
; 498.159 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.781      ;
; 498.160 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.780      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.792      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.792      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.792      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.792      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.792      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.792      ;
; 498.161 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.779      ;
; 498.163 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.777      ;
; 498.165 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.786      ;
; 498.165 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.775      ;
; 498.173 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.767      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.772      ;
; 498.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.758      ;
; 498.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.758      ;
; 498.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.758      ;
; 498.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.534      ;
; 498.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.534      ;
; 498.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.234     ; 1.534      ;
; 498.233 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.707      ;
; 498.233 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.707      ;
; 498.233 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.707      ;
; 498.234 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.706      ;
; 498.236 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.704      ;
; 498.238 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.702      ;
; 498.241 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.699      ;
; 498.242 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.698      ;
; 498.244 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.696      ;
; 498.245 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.695      ;
; 498.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.664      ;
; 498.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.474      ;
; 498.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.474      ;
; 498.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.474      ;
; 498.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.474      ;
; 498.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.474      ;
; 498.281 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.232     ; 1.474      ;
; 498.287 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.664      ;
; 498.287 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.664      ;
; 498.287 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 1.664      ;
; 498.301 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.047     ; 1.639      ;
+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                                                                              ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.106 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[30]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.430      ;
; 0.147 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mem_baddr[12]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.471      ;
; 0.148 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_mem_baddr[11]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.472      ;
; 0.149 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[17]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.473      ;
; 0.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[5]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.477      ;
; 0.151 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.477      ;
; 0.151 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.477      ;
; 0.154 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_data[3]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.480      ;
; 0.154 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[29]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.478      ;
; 0.155 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.481      ;
; 0.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.482      ;
; 0.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[10]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.483      ;
; 0.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[16]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.483      ;
; 0.157 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[12]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.484      ;
; 0.157 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[14]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.484      ;
; 0.160 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[2]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.484      ;
; 0.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_wb_rd_addr_offset[1]                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.486      ;
; 0.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[12]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.486      ;
; 0.162 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[3]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.486      ;
; 0.163 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[0]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.219      ; 0.486      ;
; 0.163 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[13]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.490      ;
; 0.163 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[15]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.490      ;
; 0.165 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_wr_data[16]                                                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.491      ;
; 0.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[27]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.490      ;
; 0.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.493      ;
; 0.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_bht_ptr_unfiltered[2]                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.219      ; 0.490      ;
; 0.170 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.496      ;
; 0.170 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[28]                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.494      ;
; 0.170 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[11]                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.223      ; 0.497      ;
; 0.174 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.500      ;
; 0.175 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[4]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.499      ;
; 0.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.505      ;
; 0.182 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[8]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.506      ;
; 0.183 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.222      ; 0.509      ;
; 0.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.044      ; 0.313      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.313      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.313      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[6]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.510      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|ic_fill_tag[7]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.220      ; 0.510      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[48]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[48]                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.000                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.000                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[0]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[0]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[1]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[1]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[2]                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_refs[2]                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[0]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[0]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[1]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[1]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[2]                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_count[2]                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.000                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.000                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.101                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_next.101                                                                                                                                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.101                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_state.101                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|init_done                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|init_done                                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|wr_address                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|wr_address                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_rd                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|jtag_rd                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_has_started                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_has_started                                                                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[1]                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[1]                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[2]                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_offset[2]                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_active                                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_xfer_rd_addr_active                                                                                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[0]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[0]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[2]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|rd_ptr[2]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[2]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[2]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|empty                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|empty                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|count[0]                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|count[0]                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_next.010000000                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_next.010000000                                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|ack_refresh_request                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|ack_refresh_request                                                                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|refresh_request                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|refresh_request                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|active_cs_n                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|active_cs_n                                                                                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[0]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[0]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[1]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|DE0_Nano_SOPC_sdram_input_efifo_module:the_DE0_Nano_SOPC_sdram_input_efifo_module|entries[1]                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|use_reg                                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter|use_reg                                                                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[1]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[1]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[2]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[2]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[0]                                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|i_cmd[0]                                                                                                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|full                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|full                                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[1]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|wr_ptr[1]                                                                                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[7]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[7]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[10]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[10]                                                                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[4]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[4]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[2]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[2]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[1]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[1]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[5]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[5]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[0]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[0]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[6]                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[6]                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[1]                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[1]                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[2]                                                                                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_rd_data_cnt[2]                                                                                                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_fill_active                                                                                                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_dc_fill_active                                                                                                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_avalon_reg:the_DE0_Nano_SOPC_cpu_nios2_avalon_reg|oci_single_step_mode                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_avalon_reg:the_DE0_Nano_SOPC_cpu_nios2_avalon_reg|oci_single_step_mode                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                             ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.315      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.323      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.317      ;
; 0.204 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.325      ;
; 0.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.326      ;
; 0.206 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.326      ;
; 0.214 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.334      ;
; 0.214 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.334      ;
; 0.216 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.337      ;
; 0.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.340      ;
; 0.223 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.344      ;
; 0.259 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.387      ;
; 0.260 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.383      ;
; 0.265 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.385      ;
; 0.266 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.268 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.388      ;
; 0.278 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.399      ;
; 0.282 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.403      ;
; 0.289 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.409      ;
; 0.295 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.416      ;
; 0.296 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.417      ;
; 0.297 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.418      ;
; 0.299 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.427      ;
; 0.305 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.425      ;
; 0.314 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.435      ;
; 0.316 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.437      ;
; 0.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.443      ;
; 0.323 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.444      ;
; 0.324 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.445      ;
; 0.324 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.445      ;
; 0.328 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.448      ;
; 0.328 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.448      ;
; 0.328 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.448      ;
; 0.328 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.449      ;
; 0.334 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.454      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.460      ;
; 0.340 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.460      ;
; 0.341 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.461      ;
; 0.346 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.467      ;
; 0.346 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.467      ;
; 0.351 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.471      ;
; 0.361 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.234      ; 0.679      ;
; 0.362 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.482      ;
; 0.363 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.483      ;
; 0.367 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.487      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.495      ;
; 0.375 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.503      ;
; 0.376 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.496      ;
; 0.376 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.496      ;
; 0.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.497      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                  ; To Node                                                                                                                                                                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 0.314      ;
; 0.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 0.314      ;
; 0.185 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 0.315      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 0.315      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_primed                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_primed                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|transmitting                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|transmitting                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|s_readdata[0]                                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|s_readdata[0]                                                                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                                                         ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[1]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|pending_response_count[0]                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|pending_response_count[0]                                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_003|has_pending_responses                                                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[1]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:gsensor_spi_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:epcs_epcs_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|SCLK_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|SCLK_reg                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|MISO_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|MISO_reg                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|EOP                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_RW                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|REG_RW                                                                                                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_scl:i2c_scl|data_out                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_scl:i2c_scl|data_out                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_dir                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_dir                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|pfdena_reg                                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|pfdena_reg                                                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_out                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_i2c_sda:i2c_sda|data_out                                                                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
; 0.192 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.313      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe4a[0]                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe5a[0]                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|wait_latency_counter[0]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|wait_latency_counter[0]                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[1]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[1]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|wait_latency_counter[0]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_sda_s1_translator|wait_latency_counter[0]                                                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|slowcount[0]                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|slowcount[0]                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|state[4]                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|state[4]                                                                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[11]                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[11]                                                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[9]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[8]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[8]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.315      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[7]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[7]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.316      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.316      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[2] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.316      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[0]                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[0]                                                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.316      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 0.325      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[2]                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[2]                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[0]                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[0]                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.317      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                                                                                                                         ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.186 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.314      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.313      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.316      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.317      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.317      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.317      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[0]                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[37]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[36]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.327      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.319      ;
; 0.201 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.320      ;
; 0.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.321      ;
; 0.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.321      ;
; 0.206 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.206 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.206 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.206 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.206 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[14]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.208 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.327      ;
; 0.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.330      ;
; 0.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.373      ;
; 0.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.373      ;
; 0.255 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                                                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                                                                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.374      ;
; 0.258 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.377      ;
; 0.259 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.378      ;
; 0.262 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[1]                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.389      ;
; 0.263 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]                                                                                                                                                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.382      ;
; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.382      ;
; 0.265 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.384      ;
; 0.266 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.385      ;
; 0.266 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[12]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.385      ;
; 0.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.386      ;
; 0.267 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.386      ;
; 0.267 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[11]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[10]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.386      ;
; 0.269 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[15]                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.388      ;
; 0.269 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.388      ;
; 0.269 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.388      ;
; 0.270 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.389      ;
; 0.270 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.389      ;
; 0.270 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.389      ;
; 0.270 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                                ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.389      ;
; 0.270 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                                                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                               ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.389      ;
; 0.270 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.389      ;
; 0.271 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.390      ;
; 0.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.391      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                          ; To Node                                                                                                                                                                                                            ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_select_i2c_clk:select_i2c_clk|data_out                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_select_i2c_clk:select_i2c_clk|data_out                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[1]                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[10]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.313      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|wait_latency_counter[0]                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 0.322      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|empty                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[31]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[15]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[27]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[11]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[20]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[4]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 0.323      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 0.323      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                                  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|readdata[0]                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]  ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.317      ;
; 0.198 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.317      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.318      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.318      ;
; 0.200 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.320      ;
; 0.201 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.321      ;
; 0.201 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:key_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.320      ;
; 0.204 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.324      ;
; 0.205 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|pending_read_count[5]                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.325      ;
; 0.207 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.326      ;
; 0.209 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.329      ;
; 0.209 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[0]                                                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:select_i2c_clk_s1_translator|wait_latency_counter[1]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.329      ;
; 0.218 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.338      ;
; 0.219 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.339      ;
; 0.220 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.339      ;
; 0.220 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.339      ;
; 0.220 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.339      ;
; 0.221 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.340      ;
; 0.225 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 0.345      ;
; 0.229 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.035      ; 0.348      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[12]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[4]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[31]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[15]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[0]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[16]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[28]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[23]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[19]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[3]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[27]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[11]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[8]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[7]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[24]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.403 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[20]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.043     ; 1.541      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[21]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[29]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[13]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[26]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[10]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[6]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[22]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[1]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[17]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[25]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[9]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[18]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[2]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[5]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.044     ; 1.538      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[14]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 3.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|Mn_rot_step2[30]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 5.000        ; -0.049     ; 1.533      ;
; 8.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[10]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.104     ; 1.720      ;
; 8.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[13]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.104     ; 1.720      ;
; 8.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[9]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.104     ; 1.720      ;
; 8.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[11]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.104     ; 1.720      ;
; 8.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[8]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.104     ; 1.720      ;
; 8.113 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[14]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.104     ; 1.720      ;
; 8.122 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[12]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.107     ; 1.708      ;
; 8.122 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[7]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.106     ; 1.709      ;
; 8.122 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[2]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.105     ; 1.710      ;
; 8.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 1.702      ;
; 8.156 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.082     ; 1.702      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[2]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[8]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[9]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[10]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[11]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[13]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[14]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.723      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.136     ; 1.644      ;
; 8.158 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[0]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.136     ; 1.644      ;
; 8.159 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[3]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.722      ;
; 8.159 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[6]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.722      ;
; 8.159 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_bank[1]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.722      ;
; 8.166 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[4]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 1.716      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[5]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.713      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[7]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.711      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[2]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.713      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[7]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.060     ; 1.712      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[12]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.711      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_bank[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.713      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_dqm[0]                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.711      ;
; 8.167 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_dqm[1]                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.711      ;
; 8.170 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[0]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.709      ;
; 8.170 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[9]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.709      ;
; 8.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[8]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.062     ; 1.706      ;
; 8.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[3]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.066     ; 1.702      ;
; 8.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[11]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.066     ; 1.702      ;
; 8.172 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[12]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.064     ; 1.704      ;
; 8.173 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_addr[10]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.068     ; 1.699      ;
; 8.174 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[3]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.120     ; 1.644      ;
; 8.178 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[4]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.701      ;
; 8.178 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[15]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.061     ; 1.701      ;
; 8.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[5]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.703      ;
; 8.179 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|m_data[6]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.703      ;
; 8.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[15]                                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.115     ; 1.643      ;
; 8.180 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[4]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.115     ; 1.643      ;
; 8.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[6]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.112     ; 1.645      ;
; 8.181 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|za_data[5]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.112     ; 1.645      ;
; 8.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.066     ; 1.734      ;
; 8.187 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.066     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[66]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[64]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[38]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[39]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.065     ; 1.734      ;
; 8.188 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.740      ;
; 8.189 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.739      ;
; 8.189 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.739      ;
; 8.189 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.059     ; 1.739      ;
; 8.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.727      ;
; 8.202 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.058     ; 1.727      ;
; 8.247 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_8                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 1.624      ;
; 8.247 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_9                                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 1.624      ;
; 8.247 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sdram:sdram|oe~_Duplicate_10                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 10.000       ; -0.057     ; 1.624      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][82]                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1]                        ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|empty                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                           ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.509 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:i2c_scl_s1_translator|read_latency_shift_reg[0]                                                                                                                            ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.039     ; 2.439      ;
; 17.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.430      ;
; 17.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.430      ;
; 17.521 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.430      ;
; 17.536 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:altpll_sys_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                                                                                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.041     ; 2.410      ;
; 17.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.409      ;
; 17.546 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.409      ;
; 17.547 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|CMD_START                                                                                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.403      ;
; 17.547 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_WRITE                                                                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.403      ;
; 17.547 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.403      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.664 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.108      ; 2.399      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a1                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a3                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a2                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|parity4                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_o57:rdptr_g|counter3a0                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[1]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[1] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[2] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[0] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|llreq                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_one                                      ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_fefifo_3dc:read_state|b_non_empty                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[1]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.674 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[0]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[0]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.281      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[3]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.277      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|rdptrrg[2]                                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.281      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe11a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe12a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[0]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[0]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[1]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[1]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[0]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[2]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[2]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|cntr_b9b:rdptr_b|counter_reg_bit[3]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rs_dbwp|dffe7a[3]                              ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|dffpipe_bd9:dffpipe_rdbuw|dffe7a[3]                                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.280      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[3]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.277      ;
; 17.675 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_rx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|altdpram:fiforam|xraddr[2]                                         ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.281      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.026     ; 2.281      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.026     ; 2.281      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[3]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.029     ; 2.278      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|parity5                                  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.029     ; 2.278      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.026     ; 2.281      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[0]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.026     ; 2.281      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[2]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.026     ; 2.281      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|write_delay_cycle[3]                                               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.029     ; 2.278      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe9a[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.029     ; 2.278      ;
; 17.680 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|FIFO_CLEAR                                                                                      ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.029     ; 2.278      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 49.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate         ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 0.992      ;
; 49.433 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0        ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 0.992      ;
; 49.447 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 0.975      ;
; 98.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 1.350      ;
; 98.774 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.176      ;
; 98.774 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.176      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.781 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.165      ;
; 98.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.143      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.144      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.135      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 1.101      ;
; 98.962 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.992      ;
; 98.962 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.992      ;
; 98.962 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.992      ;
; 98.969 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.985      ;
; 98.969 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.985      ;
; 98.969 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.985      ;
; 98.969 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.985      ;
; 98.969 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 0.985      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.978      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 98.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.954      ;
; 99.260 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.692      ;
; 99.260 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.692      ;
; 99.260 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.692      ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                  ; To Node                                                                                                                                      ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 98.210 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[1]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.048     ; 1.729      ;
; 98.210 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[3]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.048     ; 1.729      ;
; 98.210 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[2]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.048     ; 1.729      ;
; 98.210 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.048     ; 1.729      ;
; 98.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.045     ; 1.718      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.349 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.108      ; 1.714      ;
; 98.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.119      ; 1.729      ;
; 98.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.119      ; 1.729      ;
; 98.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.119      ; 1.729      ;
; 98.377 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; 0.119      ; 1.729      ;
; 98.404 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 1.526      ;
; 98.404 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|pending_response_count[0]                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 1.526      ;
; 98.404 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0]                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 1.525      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 1.525      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.058     ; 1.524      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.057     ; 1.525      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[3]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.056     ; 1.526      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.405 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.055     ; 1.527      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[1]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.410 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[0]                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.044     ; 1.533      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[0]                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|wait_latency_counter[1]                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:g_sensor_int_s1_translator|read_latency_shift_reg[0]                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.051     ; 1.525      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.052     ; 1.524      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[16]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[17]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[18]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[19]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[20]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[21]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[22]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[23]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[24]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[25]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[26]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
; 98.411 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[27]                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 100.000      ; -0.050     ; 1.526      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 248.993 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 250.000      ; -0.030     ; 0.964      ;
; 498.585 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.045     ; 1.357      ;
; 498.585 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.045     ; 1.357      ;
; 498.585 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.045     ; 1.357      ;
; 498.585 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.045     ; 1.357      ;
; 498.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 1.207      ;
; 498.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 1.207      ;
; 498.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 1.207      ;
; 498.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 1.207      ;
; 498.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 1.207      ;
; 498.743 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 1.207      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.809 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.144      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.835 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.118      ;
; 498.943 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.029     ; 1.015      ;
; 498.943 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.029     ; 1.015      ;
; 498.943 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.029     ; 1.015      ;
; 498.943 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.029     ; 1.015      ;
; 498.943 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.029     ; 1.015      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.946 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 1.007      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.979 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.972      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 498.983 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.034     ; 0.970      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.150 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.801      ;
; 499.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.154      ; 0.970      ;
; 499.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.154      ; 0.970      ;
; 499.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.154      ; 0.970      ;
; 499.171 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; 0.154      ; 0.970      ;
; 499.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 0.726      ;
; 499.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 0.726      ;
; 499.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 0.726      ;
; 499.224 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.037     ; 0.726      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
; 499.237 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 500.000      ; -0.036     ; 0.714      ;
+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.495  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.614      ;
; 0.495  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.614      ;
; 0.495  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.614      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.720  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.839      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.734  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.854      ;
; 0.740  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.861      ;
; 0.740  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.861      ;
; 0.740  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.861      ;
; 0.740  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.861      ;
; 0.740  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.861      ;
; 0.745  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.866      ;
; 0.745  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.866      ;
; 0.745  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.866      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.965      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.867  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.988      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.876  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.029      ; 0.989      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.881  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.002      ;
; 0.887  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.033      ; 1.004      ;
; 0.911  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.033      ; 1.028      ;
; 0.911  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.033      ; 1.028      ;
; 1.027  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.039      ; 1.150      ;
; 50.233 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.511      ; 0.848      ;
; 50.248 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate         ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.514      ; 0.866      ;
; 50.248 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0        ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.514      ; 0.866      ;
+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                               ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.500 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.620      ;
; 0.504 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.625      ;
; 0.504 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.625      ;
; 0.504 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.625      ;
; 0.504 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.037      ; 0.625      ;
; 0.522 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.234      ; 0.840      ;
; 0.522 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[1]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.234      ; 0.840      ;
; 0.522 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem_used[0]                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.234      ; 0.840      ;
; 0.522 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.234      ; 0.840      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.573 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.693      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.715 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.036      ; 0.835      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[8]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.718 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.840      ;
; 0.738 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.866      ;
; 0.738 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.866      ;
; 0.738 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.866      ;
; 0.738 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.866      ;
; 0.738 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.044      ; 0.866      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[9]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[7]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.741 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.864      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[9]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[11]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[7]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[10]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[8]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[4]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[6]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.039      ; 0.969      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[15]                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[2]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[3]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.862 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.038      ; 0.984      ;
; 0.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[1]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.035      ; 1.026      ;
; 0.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][1]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.035      ; 1.026      ;
; 0.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[5]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.035      ; 1.026      ;
; 0.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][5]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.035      ; 1.026      ;
; 0.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][0]                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.035      ; 1.026      ;
; 0.907 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|av_readdata_pre[0]                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.035      ; 1.026      ;
; 1.035 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.047      ; 1.166      ;
; 1.035 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000        ; 0.047      ; 1.166      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                             ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.070 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.239      ; 1.393      ;
; 1.070 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.239      ; 1.393      ;
; 1.076 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.397      ;
; 1.076 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.397      ;
; 1.076 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[4]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.397      ;
; 1.076 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr[5]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.397      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.077 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1]  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.237      ; 1.398      ;
; 1.078 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.232      ; 1.394      ;
; 1.078 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[3]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.232      ; 1.394      ;
; 1.078 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[4]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.232      ; 1.394      ;
; 1.078 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.232      ; 1.394      ;
; 1.078 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.232      ; 1.394      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.236      ; 1.401      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.236      ; 1.401      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq4                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.236      ; 1.401      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq2                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.236      ; 1.401      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq5                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.236      ; 1.401      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0]                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.228      ; 1.393      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1]                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.228      ; 1.393      ;
; 1.081 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|A_ipending_reg_irq3                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.236      ; 1.401      ;
; 1.088 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[1]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.231      ; 1.403      ;
; 1.088 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[2]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.231      ; 1.403      ;
; 1.088 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[3]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.231      ; 1.403      ;
; 1.088 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[4]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.231      ; 1.403      ;
; 1.088 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr[0]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.231      ; 1.403      ;
; 1.089 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.224      ; 1.397      ;
; 1.089 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.224      ; 1.397      ;
; 1.089 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.224      ; 1.397      ;
; 1.089 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.224      ; 1.397      ;
; 1.089 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.224      ; 1.397      ;
; 1.089 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.224      ; 1.397      ;
; 1.092 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_valid                                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.221      ; 1.397      ;
; 1.092 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[11]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.221      ; 1.397      ;
; 1.092 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[10]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.221      ; 1.397      ;
; 1.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.219      ; 1.396      ;
; 1.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.219      ; 1.396      ;
; 1.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.219      ; 1.396      ;
; 1.093 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                                                  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.219      ; 1.396      ;
; 1.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.209      ; 1.568      ;
; 1.275 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.209      ; 1.568      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|E_wr_dst_reg_from_D                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_wr_dst_reg_from_E                                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_dst_regnum[4]                                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_dst_regnum[2]                                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|M_dst_regnum[3]                                                                                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[15]                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[31]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[15]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[17]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[17]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[22]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[22]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[13]                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[12]                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[28]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[28]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[9]                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[9]                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[16]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[0]                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[16]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[13]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[13]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[13]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[12]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[3]                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[19]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[19]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[11]                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[27]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[27]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[11]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[24]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[8]                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[24]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[8]                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[2]                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[18]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[30]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|out_payload[14]                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[30]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[14]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[14]                                                                                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[14]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[6]                                                                   ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[6]                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|d_readdata_d1[6]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.043      ; 1.403      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_width_adapter:width_adapter_001|data_reg[3]                                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_iw[31]                                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
; 1.276 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|i_readdata_d1[31]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000        ; 0.042      ; 1.402      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                                                                            ; Launch Clock                                       ; Latch Clock                                        ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.234      ; 1.397      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.229      ; 1.392      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.229      ; 1.392      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.229      ; 1.392      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.229      ; 1.392      ;
; 1.079 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                              ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.229      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_master_agent:clock_crossing_io_m0_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|read_latency_shift_reg[0]                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[4]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.384      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[3]                                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.384      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.384      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                          ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.384      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.043      ; 1.391      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.384      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|force_reload                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[16]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[17]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[18]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[19]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[20]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[21]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[22]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[23]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[24]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[25]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[26]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[27]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[28]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[29]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[30]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_is_running                                                                                                                                      ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|internal_counter[31]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.044      ; 1.392      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[14]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[30]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[14]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[13]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[29]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[13]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[13]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[28]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[12]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[12]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[12]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[26]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[10]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[10]                                                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[10]                                                                                                            ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.045      ; 1.393      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[9]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[25]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[9]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[9]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[24]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[8]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[8]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[8]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.042      ; 1.390      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[7]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[7]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[23]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[7]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[7]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[6]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[6]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[22]                                                                                                                                    ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[6]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[6]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|av_readdata_pre[5]                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[5]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|readdata[5]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:timer_s1_translator|av_readdata_pre[5]                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.046      ; 1.394      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|counter_snapshot[4]                                                                                                                                     ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[1]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[1]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d1_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|d2_data_in[0]                                                                                                                                               ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                                                                             ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|readdata[0]                                                                                                                                                 ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.050      ; 1.398      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|delayed_unxcounter_is_zeroxx0                                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.264 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.041      ; 1.389      ;
; 1.265 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|read_latency_shift_reg[0]                                                                                                         ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.385      ;
; 1.265 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                        ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.385      ;
; 1.265 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000        ; 0.036      ; 1.385      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                      ; To Node                                                                                                                                                                                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.646 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.248      ; 1.978      ;
; 1.646 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.248      ; 1.978      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.249      ; 1.986      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.249      ; 1.986      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.249      ; 1.986      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[38]                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|prev_reset                                                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.653 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe6a[0]                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.242      ; 1.979      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[4]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                             ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.658 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.239      ; 1.981      ;
; 1.691 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|spi_clk                                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.210      ; 1.985      ;
; 1.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe4a[0]                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.975      ;
; 1.846 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe5a[0]                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.975      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[31]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[26]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[25]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[24]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[19]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[16]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[15]                                                                                              ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.978      ;
; 1.854 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[4]                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[0]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[0]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[1]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[1]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[2]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[2]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[3]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[3]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[4]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[4]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[5]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[5]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_space_avail[6]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|pending_read_count[6]                                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|full                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|wr_strobe                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_wr_strobe                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[9]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iEOP_reg                                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[2]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[0]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[0]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[1]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[1]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[2]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[3]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[3]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[3]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[2]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[3]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[2]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[5]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[4]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[4]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[5]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[5]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[4]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[4]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[5]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[0]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[1]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[1]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[0]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[6]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[6]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[6]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[7]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[6]                                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.975      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|tx_holding_reg[7]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|shift_reg[7]                                                                                            ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rx_holding_reg[7]                                                                                       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|rd_strobe                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[9]                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[9]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|TOE                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_rd_strobe                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|RRDY                                                                                                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|ROE                                                                                                     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|iE_reg                                                                                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 1.977      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[8]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|data_to_cpu[8]                                                                                          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:epcs_epcs_control_port_translator|av_readdata_pre[8]                                                                                               ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[7]                                                                        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.974      ;
; 1.855 ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_reg[7]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.978      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+--------------+----------------+-----------------+----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                                                                                                                                                                               ;
+-------+--------------+----------------+-----------------+----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 4.749 ; 4.979        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                             ;
; 4.749 ; 4.979        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                                   ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_data_module:DE0_Nano_SOPC_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_mdf1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                           ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_data_module:DE0_Nano_SOPC_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_mdf1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                                 ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                       ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                             ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                             ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~portb_re_reg                                                                                                                                                   ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a0~porta_address_reg0 ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a0~porta_we_reg       ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a8~porta_address_reg0 ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a8~porta_we_reg       ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_a_module:DE0_Nano_SOPC_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_2jg1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_a_module:DE0_Nano_SOPC_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_2jg1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                 ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_b_module:DE0_Nano_SOPC_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_3jg1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ;
; 4.750 ; 4.980        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_b_module:DE0_Nano_SOPC_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_3jg1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                 ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                                   ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                                         ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                             ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                                   ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                       ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_re_reg                                                                                                                                             ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_tag_module:DE0_Nano_SOPC_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_vdh1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                              ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_a_module:DE0_Nano_SOPC_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_2jg1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ;
; 4.751 ; 4.981        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_b_module:DE0_Nano_SOPC_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_3jg1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                           ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                                   ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~portb_re_reg                                                                                                                                                         ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_data_module:DE0_Nano_SOPC_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_mdf1:auto_generated|ram_block1a0~porta_bytena_reg0                                                                                                                                            ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_data_module:DE0_Nano_SOPC_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_mdf1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                            ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_data_module:DE0_Nano_SOPC_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_mdf1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                           ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                             ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_victim_module:DE0_Nano_SOPC_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                        ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                           ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                                 ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a0~porta_bytena_reg0  ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a8~porta_bytena_reg0  ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_ocimem:the_DE0_Nano_SOPC_cpu_nios2_ocimem|DE0_Nano_SOPC_cpu_ociram_sp_ram_module:DE0_Nano_SOPC_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_t381:auto_generated|ram_block1a8~porta_datain_reg0  ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_a_module:DE0_Nano_SOPC_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_2jg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_register_bank_b_module:DE0_Nano_SOPC_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_3jg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_bht_data[0]                                                                                                                                                                                                                                                                                 ;
; 4.752 ; 4.982        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|D_bht_data[1]                                                                                                                                                                                                                                                                                 ;
; 4.753 ; 4.983        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_bht_module:DE0_Nano_SOPC_cpu_bht|altsyncram:the_altsyncram|altsyncram_25h1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                                    ;
; 4.753 ; 4.983        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_dc_tag_module:DE0_Nano_SOPC_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_8pg1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                              ;
; 4.753 ; 4.983        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0                                                                 ;
; 4.753 ; 4.983        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_we_reg                                                                       ;
; 4.753 ; 4.983        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                        ;
; 4.753 ; 4.983        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                              ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                            ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                           ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_ic_data_module:DE0_Nano_SOPC_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_6ed1:auto_generated|ram_block1a0~portb_re_reg                                                                                                                                                 ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0                                                                 ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_we_reg                                                                       ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                         ;
; 4.754 ; 4.984        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                               ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_datain_reg0                                                                  ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[0]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[1]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[2]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[3]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[4]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[5]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[6]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|rdata[7]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                                         ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                         ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[0]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[10]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[11]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[12]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[13]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[14]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[15]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[17]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[1]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[22]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[25]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[28]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[2]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[30]                                                                                                                                                                                                             ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[3]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[4]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[5]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[6]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[7]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[8]                                                                                                                                                                                                              ;
; 4.755 ; 4.985        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_payload[9]                                                                                                                                                                                                              ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_r:the_DE0_Nano_SOPC_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0                                                                 ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_datain_reg0                                                                  ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|DE0_Nano_SOPC_jtag_uart_scfifo_w:the_DE0_Nano_SOPC_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0                                                                 ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                                        ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[0]                                                                                                                                                                                                             ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[10]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[11]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[12]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[13]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[14]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[15]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[16]                                                                                                                                                                                                            ;
; 4.756 ; 4.986        ; 0.230          ; Low Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_payload[17]                                                                                                                                                                                                            ;
+-------+--------------+----------------+-----------------+----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.209 ; 9.439        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_address_reg0                              ;
; 9.209 ; 9.439        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_we_reg                                    ;
; 9.210 ; 9.440        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|altsyncram:the_boot_copier_rom|altsyncram_u341:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ;
; 9.211 ; 9.441        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_10d1:auto_generated|ram_block1a0~porta_datain_reg0                               ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_00d1:auto_generated|ram_block1a0~portb_address_reg0                              ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[47]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[48]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[49]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[50]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[51]                                                                                                  ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                                                   ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                                                   ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                                                   ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                                                   ;
; 9.213 ; 9.443        ; 0.230          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                                                   ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                          ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                          ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0]                         ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                          ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0]                         ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                          ;
; 9.242 ; 9.426        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0]                         ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|DE0_Nano_SOPC_altpll_sys_stdsync_sv6:stdsync2|DE0_Nano_SOPC_altpll_sys_dffpipe_l2c:dffpipe3|dffe6a[0]                                                            ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_altpll_sys:altpll_sys_inst|prev_reset                                                                                                                                                       ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                          ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                          ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0]                         ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                          ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                         ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                           ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                                          ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                                                                              ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                                                                              ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[38]                                                                                             ;
; 9.244 ; 9.428        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                                                                             ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[0]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[1]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[2]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[3]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[4]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[5]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr[6]                                                                                                     ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                                                ;
; 9.246 ; 9.430        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                                                ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                         ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0]                        ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1]                        ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                         ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0]                        ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1]                        ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[0]                                                                                                    ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[1]                                                                                                    ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[2]                                                                                                    ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[3]                                                                                                    ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr[4]                                                                                                    ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                                               ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                                               ;
; 9.259 ; 9.443        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[12]                                                                                                        ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[13]                                                                                                        ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|endofpacketvalue_reg[14]                                                                                                        ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[10]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[11]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[12]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[13]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[14]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[15]                                                                                               ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[8]                                                                                                ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|epcs_slave_select_holding_reg[9]                                                                                                ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[0]                             ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[1]                             ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|a_graycounter_tc6:wrptr_g|counter6a[2]                             ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[0] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[1] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[2] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe10a[3] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[0] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[1] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[2] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe11a[3] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[0] ;
; 9.270 ; 9.454        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|gsensor_fifo:gsensor_fifo_tx|dcfifo:dcfifo_component|dcfifo_v2j1:auto_generated|alt_synch_pipe_kc8:dffpipe_ws_dgrp|dffpipe_nd9:dffpipe8|dffe12a[1] ;
+-------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.315 ; 49.531       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                          ;
; 49.315 ; 49.531       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tdo~reg0                                                                                                                                                                                                                         ;
; 49.315 ; 49.531       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                                                                               ;
; 49.334 ; 49.518       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ;
; 49.334 ; 49.518       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ;
; 49.334 ; 49.518       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[1]                                                    ;
; 49.343 ; 49.527       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[36]                                                       ;
; 49.343 ; 49.527       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[37]                                                       ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.000                                                   ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.010                                                   ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|DRsize.100                                                   ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[1]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[2]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[31]                                                       ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[3]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[4]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[5]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[6]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[7]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[8]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[9]                                                        ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]                                                                                                                                                                                                                                                                                 ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]                                                                                                                                                                                                                                                                                 ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]                                                                                                                                                                                                                                                                                 ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]                                                                                                                                                                                                                                                                                 ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                                 ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|ir_out[0]                                                    ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[0]                                                        ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[10]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[11]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[12]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[13]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[14]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[15]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[16]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[17]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[18]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[19]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[20]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[21]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[22]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[23]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[24]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[25]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[26]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[27]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[28]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[29]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[30]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[32]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[33]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[34]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|sr[35]                                                       ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[0]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[1]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[2]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[3]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[4]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[5]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[6]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[7]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[8]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|count[9]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read                                                                                                                                                                                                                             ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|read_req                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|state                                                                                                                                                                                                                            ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|tck_t_dav                                                                                                                                                                                                                        ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[0]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[10]                                                                                                                                                                                                                     ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[1]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[2]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[3]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[4]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[5]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[6]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[7]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[8]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|td_shift[9]                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                  ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[0]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[1]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[2]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[3]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[5]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|wdata[7]                                                                                                                                                                                                                         ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write                                                                                                                                                                                                                            ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                    ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_jtag_uart:jtag_uart|alt_jtag_atlantic:DE0_Nano_SOPC_jtag_uart_alt_jtag_atlantic|write_valid                                                                                                                                                                                                                      ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                                                                                                                                                           ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                                                                                ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                                                                                ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                                                                                ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                                                                                ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                                                                              ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                                                                              ;
; 49.359 ; 49.543       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]'                                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.751 ; 49.981       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~porta_address_reg0      ;
; 49.751 ; 49.981       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~porta_we_reg            ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0|altsyncram_mvc1:auto_generated|ram_block1a0~portb_address_reg0      ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                          ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                           ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                           ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                           ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                           ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                           ;
; 49.753 ; 49.983       ; 0.230          ; Low Pulse Width  ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_gvc1:auto_generated|ram_block1a0~porta_datain_reg0       ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[0]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[1]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[2]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d1_data_in[3]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[0]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[1]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[2]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|d2_data_in[3]                                                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                                                                              ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                                                                              ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                                                                              ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                              ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[0]                                                                                                                                                  ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[1]                                                                                                                                                  ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[2]                                                                                                                                                  ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|readdata[3]                                                                                                                                                  ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_valid                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|old_read                                                                                                                ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                       ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                                        ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                                        ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                                        ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                       ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                       ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][45]                                                                          ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                          ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79]                                                                          ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                         ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                         ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|read_latency_shift_reg[0]                                                                                                        ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[0]                                                                                                          ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sw_s1_translator|wait_latency_counter[1]                                                                                                          ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0]                                                                                          ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0]                                                                                            ;
; 49.781 ; 49.997       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]                                                                                            ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[10]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[11]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[12]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[13]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[14]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[15]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[16]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[17]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[18]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[19]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[20]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[37]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[38]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[42]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[43]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[44]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[45]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[46]                                                                          ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[5]                                                                           ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[6]                                                                           ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[7]                                                                           ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[8]                                                                           ;
; 49.782 ; 50.012       ; 0.230          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_payload[9]                                                                           ;
; 49.782 ; 49.998       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][45]                                                                                        ;
; 49.782 ; 49.998       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79]                                                                          ;
; 49.782 ; 49.998       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[0]                                                                                                         ;
; 49.782 ; 49.998       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:led_s1_translator|wait_latency_counter[1]                                                                                                         ;
; 49.782 ; 49.998       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|has_pending_responses                                                                                                                  ;
; 49.782 ; 49.998       ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_traffic_limiter:limiter_002|last_channel[3]                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]'                                                                                                                                                                                                                       ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock                                              ; Clock Edge ; Target                                                                                                                                                                                ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 249.776 ; 249.992      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|oDIN                                                                                            ;
; 249.776 ; 249.992      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Fall       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_ack                                                                                        ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[0]                                                                                                             ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[1]                                                                                                             ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Channel[2]                                                                                                             ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start                                                                                                                  ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][100]                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101]                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65]                                               ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][100]                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101]                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65]                                               ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[100]                                   ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[64]                                    ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[65]                                    ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[66]                                    ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|read_latency_shift_reg[0]                                                               ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[0]                                                                 ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|wait_latency_counter[1]                                                                 ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_merlin_slave_translator:adc_spi_read_slave_translator|waitrequest_reset_override                                                              ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                         ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                         ;
; 249.780 ; 249.996      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                        ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[0]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[1]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[2]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_cont[3]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[0]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[10]                                                                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[11]                                                                                   ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[1]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[2]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[3]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[4]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[5]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[6]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[7]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[8]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|read_data[9]                                                                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_00                                                                                        ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_01                                                                                        ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02                                                                                        ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_03                                                                                        ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[0]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[10]                                                                                                         ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[11]                                                                                                         ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[15]                                                                                                         ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[1]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[2]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[3]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[4]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[5]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[6]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[7]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[8]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|s_readdata[9]                                                                                                          ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][0]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][10]                                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][11]                                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][15]                                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][1]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][2]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][3]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][4]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][5]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][6]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][7]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][8]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[0][9]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][10]                                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][11]                                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][15]                                             ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][2]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][3]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][4]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][6]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][7]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][8]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_sc_fifo:adc_spi_read_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|mem[1][9]                                              ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[0]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[15]                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[1]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_buffer[2]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[0]                                      ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[100]                                    ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[10]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[11]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[15]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[1]                                      ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[2]                                      ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[3]                                      ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[4]                                      ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[5]                                      ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[65]                                     ;
; 249.781 ; 249.997      ; 0.216          ; High Pulse Width ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; Rise       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_buffer[6]                                      ;
+---------+--------------+----------------+------------------+----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                 ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; 0.986 ; 1.750 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 1.087 ; 1.868 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; 0.624 ; 1.175 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 0.624 ; 1.175 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 0.624 ; 1.175 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 0.607 ; 1.156 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 0.619 ; 1.170 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 0.614 ; 1.165 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 0.611 ; 1.162 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 0.611 ; 1.162 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 0.608 ; 1.157 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 0.606 ; 1.155 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 0.606 ; 1.155 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 0.606 ; 1.155 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 0.606 ; 1.155 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 0.609 ; 1.158 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 0.606 ; 1.155 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 0.606 ; 1.155 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 0.614 ; 1.165 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; 1.673 ; 2.129 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; 2.612 ; 3.417 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; 2.612 ; 3.417 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; 1.556 ; 2.062 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; 1.892 ; 2.323 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; 1.725 ; 2.189 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; 1.774 ; 2.190 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; 1.892 ; 2.323 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; 1.720 ; 2.186 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; 1.218 ; 1.707 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.348 ; 1.714 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; 3.275 ; 3.693 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; -0.772 ; -1.520 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; -0.841 ; -1.601 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; -0.316 ; -0.867 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; -0.316 ; -0.867 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; -0.301 ; -0.850 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; -0.311 ; -0.862 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; -0.307 ; -0.858 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; -0.303 ; -0.854 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; -0.303 ; -0.854 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; -0.302 ; -0.851 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; -0.303 ; -0.852 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; -0.300 ; -0.849 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; -0.307 ; -0.858 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; -1.165 ; -1.584 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; -0.809 ; -1.297 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; -1.970 ; -2.752 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; -0.809 ; -1.297 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; -0.970 ; -1.417 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; -0.979 ; -1.426 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; -1.173 ; -1.580 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; -1.134 ; -1.549 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; -0.970 ; -1.417 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; -0.740 ; -1.214 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; 0.232  ; -0.173 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; -0.608 ; -0.972 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                         ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 3.978  ; 4.095  ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 3.343  ; 3.452  ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 4.671  ; 4.672  ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 5.383  ; 5.315  ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 4.365  ; 4.311  ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 1.759  ; 1.687  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 1.759  ; 1.687  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 1.694  ; 1.639  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 1.691  ; 1.636  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 1.689  ; 1.634  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 1.677  ; 1.626  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 1.759  ; 1.687  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 1.752  ; 1.680  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 1.754  ; 1.682  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 1.676  ; 1.625  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 1.691  ; 1.636  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 1.757  ; 1.685  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 3.225  ; 2.931  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 1.762  ; 1.690  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 1.749  ; 1.677  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 1.749  ; 1.677  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 1.691  ; 1.636  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 1.674  ; 1.623  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 1.758  ; 1.686  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 1.762  ; 1.690  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 1.762  ; 1.690  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 1.690  ; 1.635  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 1.689  ; 1.634  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 1.692  ; 1.637  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 1.758  ; 1.686  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 1.689  ; 1.634  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 1.689  ; 1.634  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 1.689  ; 1.634  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 1.757  ; 1.685  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 1.757  ; 1.685  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; -0.166 ;        ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;        ; -0.195 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 3.826  ; 3.869  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 4.820  ; 4.824  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 2.677  ; 2.752  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 2.988  ; 3.095  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 3.133  ; 3.266  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 2.479  ; 2.520  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 3.071  ; 3.221  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 4.820  ; 4.824  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 3.070  ; 3.222  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 4.367  ; 4.266  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 2.756  ; 2.777  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 3.073  ; 3.061  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 2.663  ; 2.717  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;        ; 2.561  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 6.757  ; 7.254  ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                 ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 3.851  ; 3.964  ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 3.226  ; 3.332  ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 3.982  ; 4.073  ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 4.198  ; 4.134  ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 4.066  ; 4.017  ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 1.433  ; 1.383  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 1.451  ; 1.396  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 1.435  ; 1.385  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 1.509  ; 1.438  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 1.511  ; 1.440  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 1.433  ; 1.383  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 1.515  ; 1.444  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 2.983  ; 2.689  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 1.431  ; 1.381  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 1.506  ; 1.435  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 1.506  ; 1.435  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 1.431  ; 1.381  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 1.519  ; 1.448  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 1.519  ; 1.448  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 1.448  ; 1.393  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 1.515  ; 1.444  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 1.514  ; 1.443  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; -0.439 ;        ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;        ; -0.469 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 3.301  ; 3.321  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 2.161  ; 2.198  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 2.351  ; 2.421  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 2.650  ; 2.750  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 2.789  ; 2.915  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 2.161  ; 2.198  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 2.734  ; 2.875  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 4.470  ; 4.463  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 2.730  ; 2.874  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 4.035  ; 3.928  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 2.340  ; 2.427  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 2.177  ; 2.697  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 2.337  ; 2.385  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;        ; 2.245  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 5.562  ; 6.056  ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                         ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 3.951 ; 3.858 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 1.555 ; 1.490 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 1.630 ; 1.537 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 1.630 ; 1.537 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 1.567 ; 1.493 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 1.555 ; 1.490 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 1.639 ; 1.546 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 1.643 ; 1.550 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 1.643 ; 1.550 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 1.566 ; 1.492 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 1.568 ; 1.494 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 1.568 ; 1.494 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 1.568 ; 1.494 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 1.568 ; 1.494 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 1.565 ; 1.491 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 1.568 ; 1.494 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 1.568 ; 1.494 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 1.639 ; 1.546 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                 ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 3.787 ; 3.694 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 1.313 ; 1.248 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 1.388 ; 1.295 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 1.388 ; 1.295 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 1.326 ; 1.252 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 1.313 ; 1.248 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 1.398 ; 1.305 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 1.401 ; 1.308 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 1.401 ; 1.308 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 1.325 ; 1.251 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 1.327 ; 1.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 1.327 ; 1.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 1.327 ; 1.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 1.327 ; 1.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 1.324 ; 1.250 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 1.327 ; 1.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 1.327 ; 1.253 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 1.398 ; 1.305 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-------+-------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 4.003     ; 4.096     ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 1.510     ; 1.584     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 1.569     ; 1.662     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 1.569     ; 1.662     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 1.512     ; 1.586     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 1.522     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 1.578     ; 1.671     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 1.582     ; 1.675     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 1.582     ; 1.675     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 1.511     ; 1.585     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 1.513     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 1.513     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 1.513     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 1.513     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 1.510     ; 1.584     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 1.513     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 1.513     ; 1.587     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 1.578     ; 1.671     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                        ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                    ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+
; I2C_SDAT     ; CLOCK_50   ; 3.819     ; 3.912     ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]   ; CLOCK_50   ; 1.269     ; 1.343     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]  ; CLOCK_50   ; 1.326     ; 1.419     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]  ; CLOCK_50   ; 1.326     ; 1.419     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]  ; CLOCK_50   ; 1.271     ; 1.345     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]  ; CLOCK_50   ; 1.279     ; 1.344     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]  ; CLOCK_50   ; 1.336     ; 1.429     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]  ; CLOCK_50   ; 1.339     ; 1.432     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]  ; CLOCK_50   ; 1.339     ; 1.432     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]  ; CLOCK_50   ; 1.270     ; 1.344     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]  ; CLOCK_50   ; 1.272     ; 1.346     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]  ; CLOCK_50   ; 1.272     ; 1.346     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10] ; CLOCK_50   ; 1.272     ; 1.346     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11] ; CLOCK_50   ; 1.272     ; 1.346     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12] ; CLOCK_50   ; 1.269     ; 1.343     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13] ; CLOCK_50   ; 1.272     ; 1.346     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14] ; CLOCK_50   ; 1.272     ; 1.346     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15] ; CLOCK_50   ; 1.336     ; 1.429     ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
+--------------+------------+-----------+-----------+------------+----------------------------------------------------+


----------------
; MTBF Summary ;
----------------
Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.

Number of Synchronizer Chains Found: 64
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
Worst Case Available Settling Time: 17.013 ns

Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+
; Source Node                                                                                                                                                                                              ; Synchronization Node                                                                                                                                                                                                                                                                                                                                                 ; Typical MTBF (Years)   ; Included in Design MTBF ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ; Greater than 1 Billion ; Yes                     ;
;                                                                                                                                                                                                          ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                ; Greater than 1 Billion ; Yes                     ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                              ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                                                                        ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                                                                     ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                                                                       ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                                                                          ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                                ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                   ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1       ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1       ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                              ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                     ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                               ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1                                                                                                                                                    ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                                   ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                                            ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                                                                                                                                                                 ; Greater than 1 Billion ; Yes                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+


Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 17.013                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                              ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 9.381        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 7.632        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 17.081                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 0.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 9.384        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 7.697        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                       ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                       ; 17.336                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                          ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                          ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 9.422        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 7.914        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 17.523                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 0.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 9.427        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 8.096        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #5: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                    ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                           ; 19.145                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                              ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                                   ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                      ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1  ;                        ;              ;                  ; 9.577        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ;                        ;              ;                  ; 9.568        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #6: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                   ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                 ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ;                                                                                                                                                                                                                                                       ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                   ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                   ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                            ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                            ; 19.147                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                               ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                     ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                   ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                     ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1  ;                        ;              ;                  ; 9.576        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ;                        ;              ;                  ; 9.571        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #7: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                    ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                           ; 19.150                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                              ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                                   ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                                      ;                        ;              ;                  ;              ;
;  sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1  ;                        ;              ;                  ; 9.579        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk:the_DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ;                        ;              ;                  ; 9.571        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #8: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.280                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.573        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 8.135        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #9: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 27.322                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.383        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.579        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 8.360        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #10: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.388                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 9.577        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 9.580        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 8.231        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #11: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.390                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[6]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;                        ;              ;                  ; 9.577        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;                        ;              ;                  ; 9.581        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[6].u|dreg[1] ;                        ;              ;                  ; 8.232        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #12: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.432                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.571        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.505        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 8.356        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #13: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.476                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.571        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 8.333        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #14: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.505                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.578        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.511        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 8.416        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #15: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.626                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.569        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.485        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #16: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 27.661                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.383        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.510        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 8.768        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #17: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.666                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[5]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 9.568        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 9.506        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 8.592        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #18: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.748                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.506        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 8.670        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #19: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.810                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 9.373        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 9.514        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 8.923        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #20: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 27.852                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 9.507        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 8.773        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #21: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                     ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                   ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                             ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                  ;
; Included in Design MTBF ; Yes                                                                                                                                                     ;
+-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                     ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                              ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                              ; 27.882                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                 ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                       ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                       ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|timeout_occurred                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_timer:timer|control_register[0]                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.571        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.569        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.742        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #22: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 27.918                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.570        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.505        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.843        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #23: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                           ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 27.967                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|irq_mask                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_g_sensor_int:g_sensor_int|edge_capture                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.579        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.579        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_003|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 8.809        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #24: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 27.985                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.380        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.510        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 9.095        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #25: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 28.017                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.571        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.507        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 8.939        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #26: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 28.029                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.504        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 8.953        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #27: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 28.133                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 9.372        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 9.512        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 9.249        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #28: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 28.133                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.381        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.579        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.173        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #29: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 28.259                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[3]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[3]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[2]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[2]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[1]                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[1]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|irq_mask[0]                                                                                             ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_sw:sw|edge_capture[0]                                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.568        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_002|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.119        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #30: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 28.301                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.572        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.569        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.160        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #31: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 28.305                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.372        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.515        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 9.418        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #32: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 28.306                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.369        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.511        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.426        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #33: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 28.315                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 9.380        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 9.513        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 9.422        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #34: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 28.471                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 1.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                           ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[1]                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[1]                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|edge_capture[0]                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_key:key|irq_mask[0]                                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.577        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.576        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_001|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.318        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #35: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                       ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                      ;
; Included in Design MTBF ; Yes                                                                                                                                                         ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                      ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                         ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                          ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                  ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                  ; 28.575                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                     ; 6.25                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                  ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                     ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Synchronization Clock                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                           ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Asynchronous Source                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_epcs:epcs|DE0_Nano_SOPC_epcs_sub:the_DE0_Nano_SOPC_epcs_sub|irq_reg                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 9.570        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 9.571        ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_irq_clock_crosser:irq_synchronizer_004|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 9.434        ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #36: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 38.027                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                              ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 19.512       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_002|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 18.515       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #37: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                              ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                       ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                       ; 38.156                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                          ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 19.571       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 18.585       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #38: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 56.740                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 19.569       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 19.370       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 17.801       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #39: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 56.816                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 19.568       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 19.369       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 17.879       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #40: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 56.934                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 19.369       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 19.510       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 18.055       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #41: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 56.952                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[6]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|din_s1  ;                        ;              ;                  ; 19.570       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[0] ;                        ;              ;                  ; 19.368       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[6].u|dreg[1] ;                        ;              ;                  ; 18.014       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #42: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 57.434                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 19.568       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 19.370       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 18.496       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #43: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 57.556                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 19.369       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 19.514       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 18.673       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #44: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 57.581                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                           ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 19.570       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 19.367       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 18.644       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #45: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.625                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 19.578       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 19.576       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 18.471       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #46: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.627                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 19.571       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 19.505       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 18.551       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #47: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 57.800                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 19.571       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 19.503       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 18.726       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #48: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 58.506                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 19.578       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 19.509       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 19.419       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #49: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                              ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                             ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                             ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                 ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                         ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                         ; 58.582                 ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                            ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                         ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                  ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  CLOCK_50                                                                                                                                                                                                            ;                        ; 20.000       ; 50.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 19.578       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 19.579       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io2|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 19.425       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #50: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                          ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                                                                                          ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                         ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                         ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                            ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                             ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                     ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                     ; 198.369                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                        ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                              ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                             ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|hbreak_enabled                                                                                                                                                                                                                                                                                           ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1  ;                        ;              ;                  ; 99.572       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ;                        ;              ;                  ; 98.797       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #51: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                                                                                                                                                                          ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready                                                                                                                                                       ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                                                                                                                                                                         ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                                                                                                                                                                         ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                                                                                                                                                                            ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                                                                                                                                                             ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                                                                                                                                                                     ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                                                                                                                                                                     ; 198.915                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                                                                                                                                                                        ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                                                                                                                                                                     ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                                                                                                                                                              ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                                                                                                                                                                            ;                        ;              ;                  ;              ;
;  altera_reserved_tck                                                                                                                                                                                                                                                                                                                                             ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_nios2_oci_debug:the_DE0_Nano_SOPC_cpu_nios2_oci_debug|monitor_ready                                                                                                                                                        ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1  ;                        ;              ;                  ; 99.579       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|DE0_Nano_SOPC_cpu:cpu|DE0_Nano_SOPC_cpu_nios2_oci:the_DE0_Nano_SOPC_cpu_nios2_oci|DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper:the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper|DE0_Nano_SOPC_cpu_jtag_debug_module_tck:the_DE0_Nano_SOPC_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ;                        ;              ;                  ; 99.336       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #52: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 296.974                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[4]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 99.381       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 99.576       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 98.017       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #53: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 296.994                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[3]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 99.379       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 99.581       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 98.034       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #54: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 297.107                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[2]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 99.382       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 99.513       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 98.212       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #55: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 297.138                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[5]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|din_s1  ;                        ;              ;                  ; 99.382       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[0] ;                        ;              ;                  ; 99.579       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[5].u|dreg[1] ;                        ;              ;                  ; 98.177       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #56: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.378                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[4]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|din_s1  ;                        ;              ;                  ; 99.384       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[0] ;                        ;              ;                  ; 99.576       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[4].u|dreg[1] ;                        ;              ;                  ; 98.418       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #57: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 297.404                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[3]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|din_s1  ;                        ;              ;                  ; 99.572       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[0] ;                        ;              ;                  ; 99.507       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[3].u|dreg[1] ;                        ;              ;                  ; 98.325       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #58: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 297.575                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[1]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 99.380       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 99.575       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 98.620       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #59: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                            ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                      ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                           ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                              ;
+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                           ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                              ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                               ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                       ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                       ; 297.721                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                          ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                       ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|out_rd_ptr_gray[0]                                                                       ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                          ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 99.383       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 99.511       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 98.827       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #60: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 298.184                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[2]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|din_s1  ;                        ;              ;                  ; 99.579       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[0] ;                        ;              ;                  ; 99.514       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[2].u|dreg[1] ;                        ;              ;                  ; 99.091       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #61: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 298.356                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[1]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|din_s1  ;                        ;              ;                  ; 99.579       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[0] ;                        ;              ;                  ; 99.513       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[1].u|dreg[1] ;                        ;              ;                  ; 99.264       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #62: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                                             ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                                                            ;
; Included in Design MTBF ; Yes                                                                                                                                                                                                               ;
+-------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                                                            ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                                               ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                                                ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                                                        ; 3                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                                                        ; 298.734                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                                                           ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                                                        ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                                                 ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                                               ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]                                                                                                                                                                 ;                        ; 100.000      ; 10.0 MHz         ;              ;
; Asynchronous Source                                                                                                                                                                                                 ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|in_wr_ptr_gray[0]                                                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|din_s1  ;                        ;              ;                  ; 99.579       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[0] ;                        ;              ;                  ; 99.578       ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_mm_clock_crossing_bridge:clock_crossing_io|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer:sync[0].u|dreg[1] ;                        ;              ;                  ; 99.577       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #63: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                               ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 997.278                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|out_data_toggle_flopped                                ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|din_s1  ;                        ;              ;                  ; 499.506      ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_003|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:out_to_in_synchronizer|dreg[0] ;                        ;              ;                  ; 497.772      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



Synchronizer Chain #64: Typical MTBF is Greater than 1 Billion Years
===============================================================================
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Chain Summary                                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Property                ; Value                                                                                                                                                                                ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source Node             ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                        ;
; Synchronization Node    ; DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1 ;
; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                               ;
; Included in Design MTBF ; Yes                                                                                                                                                                                  ;
+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Statistics                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Property                                                                                                                                                                               ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
; Method of Synchronizer Identification                                                                                                                                                  ; User Specified         ;              ;                  ;              ;
; Typical MTBF (years)                                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
; Number of Synchronization Registers in Chain                                                                                                                                           ; 2                      ;              ;                  ;              ;
; Available Settling Time (ns)                                                                                                                                                           ; 997.983                ;              ;                  ;              ;
; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                              ; 12.5                   ;              ;                  ;              ;
; Source Clock                                                                                                                                                                           ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]                                                                                                                                    ;                        ; 10.000       ; 100.0 MHz        ;              ;
; Synchronization Clock                                                                                                                                                                  ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]                                                                                                                                    ;                        ; 500.000      ; 2.0 MHz          ;              ;
; Asynchronous Source                                                                                                                                                                    ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|in_data_toggle                                         ;                        ;              ;                  ;              ;
; Synchronization Registers                                                                                                                                                              ;                        ;              ;                  ;              ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|din_s1  ;                        ;              ;                  ; 499.513      ;
;  DE0_Nano_SOPC:DE0_Nano_SOPC_inst|altera_avalon_st_handshake_clock_crosser:crosser_001|altera_avalon_st_clock_crosser:clock_xer|altera_std_synchronizer:in_to_out_synchronizer|dreg[0] ;                        ;              ;                  ; 498.470      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+



+------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                              ;
+-----------------------------------------------------+---------+-------+----------+---------+---------------------+
; Clock                                               ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+-----------------------------------------------------+---------+-------+----------+---------+---------------------+
; Worst-case Slack                                    ; 1.695   ; 0.106 ; 2.275    ; 0.495   ; 4.695               ;
;  CLOCK_50                                           ; 9.964   ; 0.185 ; 15.840   ; 1.646   ; 9.209               ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 1.695   ; 0.106 ; 2.275    ; 1.070   ; 4.695               ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 87.442  ; 0.187 ; 96.973   ; 1.079   ; 49.738              ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 247.819 ; 0.179 ; 248.245  ; 0.500   ; 249.743             ;
;  altera_reserved_tck                                ; 47.209  ; 0.186 ; 48.469   ; 0.495   ; 49.315              ;
; Design-wide TNS                                     ; 0.0     ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  CLOCK_50                                           ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  altera_reserved_tck                                ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+-----------------------------------------------------+---------+-------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                 ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; 1.776 ; 2.279 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 1.918 ; 2.474 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; 1.087 ; 1.338 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 1.087 ; 1.338 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 1.087 ; 1.338 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 1.051 ; 1.301 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 1.080 ; 1.331 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 1.075 ; 1.326 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 1.073 ; 1.324 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 1.073 ; 1.324 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 1.052 ; 1.302 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 1.052 ; 1.302 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 1.049 ; 1.299 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 1.075 ; 1.326 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; 2.830 ; 3.014 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; 4.543 ; 5.103 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; 4.543 ; 5.103 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; 2.658 ; 2.949 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; 3.210 ; 3.391 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; 2.916 ; 3.160 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; 2.925 ; 3.088 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; 3.210 ; 3.391 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; 2.882 ; 3.164 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; 2.025 ; 2.251 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; 2.992 ; 3.270 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; 7.505 ; 7.654 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_DATA0          ; CLOCK_50            ; -0.772 ; -1.520 ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; -0.841 ; -1.601 ; Rise       ; CLOCK_50                                           ;
; DRAM_DQ[*]          ; CLOCK_50            ; -0.300 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; -0.316 ; -0.728 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; -0.316 ; -0.728 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; -0.301 ; -0.699 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; -0.311 ; -0.720 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; -0.307 ; -0.715 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; -0.303 ; -0.711 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; -0.303 ; -0.711 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; -0.302 ; -0.700 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; -0.300 ; -0.697 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; -0.300 ; -0.697 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; -0.300 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; -0.300 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; -0.303 ; -0.700 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; -0.300 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; -0.300 ; -0.696 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; -0.307 ; -0.715 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; G_SENSOR_INT        ; CLOCK_50            ; -1.165 ; -1.584 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; KEY[*]              ; CLOCK_50            ; -0.809 ; -1.297 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[0]             ; CLOCK_50            ; -1.970 ; -2.752 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  KEY[1]             ; CLOCK_50            ; -0.809 ; -1.297 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; SW[*]               ; CLOCK_50            ; -0.970 ; -1.417 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[0]              ; CLOCK_50            ; -0.979 ; -1.426 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[1]              ; CLOCK_50            ; -1.173 ; -1.580 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[2]              ; CLOCK_50            ; -1.134 ; -1.549 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  SW[3]              ; CLOCK_50            ; -0.970 ; -1.417 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_SDAT            ; CLOCK_50            ; -0.740 ; -1.214 ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdi ; altera_reserved_tck ; 0.232  ; -0.173 ; Rise       ; altera_reserved_tck                                ;
; altera_reserved_tms ; altera_reserved_tck ; -0.608 ; -0.972 ; Rise       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                         ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 6.815  ; 6.843  ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 5.815  ; 5.885  ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 7.979  ; 7.901  ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 9.144  ; 9.004  ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 7.529  ; 7.410  ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 2.831  ; 2.744  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 2.828  ; 2.741  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 2.818  ; 2.736  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 2.938  ; 2.853  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 2.940  ; 2.855  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 2.816  ; 2.734  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 2.828  ; 2.741  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 2.829  ; 2.742  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 2.945  ; 2.860  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 4.850  ; 4.486  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 2.947  ; 2.862  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 2.933  ; 2.848  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 2.933  ; 2.848  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 2.828  ; 2.741  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 2.813  ; 2.731  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 2.947  ; 2.862  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 2.947  ; 2.862  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 2.827  ; 2.740  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 2.830  ; 2.743  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 2.946  ; 2.861  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 2.826  ; 2.739  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 2.945  ; 2.860  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 2.942  ; 2.857  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; 0.856  ;        ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;        ; 0.758  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 6.503  ; 6.461  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 7.681  ; 7.573  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 4.603  ; 4.579  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 5.117  ; 5.117  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 5.392  ; 5.378  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 4.275  ; 4.222  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 5.220  ; 5.379  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 7.681  ; 7.573  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 5.282  ; 5.330  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 6.918  ; 6.656  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 4.727  ; 4.639  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 5.306  ; 5.132  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 4.529  ; 4.491  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;        ; 4.178  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 11.688 ; 12.232 ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                 ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+
; EPCS_ASDO           ; CLOCK_50            ; 3.851  ; 3.964  ; Rise       ; CLOCK_50                                           ;
; EPCS_DCLK           ; CLOCK_50            ; 3.226  ; 3.332  ; Rise       ; CLOCK_50                                           ;
; EPCS_NCSO           ; CLOCK_50            ; 3.982  ; 4.073  ; Rise       ; CLOCK_50                                           ;
; I2C_SCLK            ; CLOCK_50            ; 4.198  ; 4.134  ; Rise       ; CLOCK_50                                           ;
; I2C_SDAT            ; CLOCK_50            ; 4.066  ; 4.017  ; Rise       ; CLOCK_50                                           ;
; DRAM_ADDR[*]        ; CLOCK_50            ; 1.433  ; 1.383  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[0]       ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[1]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[2]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[3]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[4]       ; CLOCK_50            ; 1.451  ; 1.396  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[5]       ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[6]       ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[7]       ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[8]       ; CLOCK_50            ; 1.435  ; 1.385  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[9]       ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[10]      ; CLOCK_50            ; 1.509  ; 1.438  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[11]      ; CLOCK_50            ; 1.511  ; 1.440  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_ADDR[12]      ; CLOCK_50            ; 1.433  ; 1.383  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_BA[*]          ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[0]         ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_BA[1]         ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CAS_N          ; CLOCK_50            ; 1.515  ; 1.444  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CS_N           ; CLOCK_50            ; 2.983  ; 2.689  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQ[*]          ; CLOCK_50            ; 1.431  ; 1.381  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[0]         ; CLOCK_50            ; 1.506  ; 1.435  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[1]         ; CLOCK_50            ; 1.506  ; 1.435  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[2]         ; CLOCK_50            ; 1.449  ; 1.394  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[3]         ; CLOCK_50            ; 1.431  ; 1.381  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[4]         ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[5]         ; CLOCK_50            ; 1.519  ; 1.448  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[6]         ; CLOCK_50            ; 1.519  ; 1.448  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[7]         ; CLOCK_50            ; 1.448  ; 1.393  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[8]         ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[9]         ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[10]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[11]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[12]        ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[13]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[14]        ; CLOCK_50            ; 1.450  ; 1.395  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQ[15]        ; CLOCK_50            ; 1.516  ; 1.445  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_DQM[*]         ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[0]        ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
;  DRAM_DQM[1]        ; CLOCK_50            ; 1.447  ; 1.392  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_RAS_N          ; CLOCK_50            ; 1.515  ; 1.444  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_WE_N           ; CLOCK_50            ; 1.514  ; 1.443  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ;
; DRAM_CLK            ; CLOCK_50            ; -0.439 ;        ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; DRAM_CLK            ; CLOCK_50            ;        ; -0.469 ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1] ;
; I2C_SCLK            ; CLOCK_50            ; 3.301  ; 3.321  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; LED[*]              ; CLOCK_50            ; 2.161  ; 2.198  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[0]             ; CLOCK_50            ; 2.351  ; 2.421  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[1]             ; CLOCK_50            ; 2.650  ; 2.750  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[2]             ; CLOCK_50            ; 2.789  ; 2.915  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[3]             ; CLOCK_50            ; 2.161  ; 2.198  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[4]             ; CLOCK_50            ; 2.734  ; 2.875  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[5]             ; CLOCK_50            ; 4.470  ; 4.463  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[6]             ; CLOCK_50            ; 2.730  ; 2.874  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
;  LED[7]             ; CLOCK_50            ; 4.035  ; 3.928  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ;
; ADC_CS_N            ; CLOCK_50            ; 2.340  ; 2.427  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ; 2.177  ; 2.697  ; Rise       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SADDR           ; CLOCK_50            ; 2.337  ; 2.385  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; ADC_SCLK            ; CLOCK_50            ;        ; 2.245  ; Fall       ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ;
; altera_reserved_tdo ; altera_reserved_tck ; 5.562  ; 6.056  ; Fall       ; altera_reserved_tck                                ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                 ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; LED[0]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[1]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[2]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[3]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[4]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[5]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[6]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED[7]              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_ADDR[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_BA[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_BA[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_CAS_N          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_CKE            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_CLK            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_CS_N           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQM[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQM[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_RAS_N          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_WE_N           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; EPCS_ASDO           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; EPCS_DCLK           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; EPCS_NCSO           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; G_SENSOR_CS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADC_CS_N            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADC_SADDR           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADC_SCLK            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[0]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[1]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[2]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[3]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[4]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[5]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[6]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[7]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[8]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[9]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[10]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[11]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_2[12]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[0]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[1]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[2]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[3]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[4]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[5]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[6]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[7]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[8]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[9]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[10]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[11]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[12]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[13]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[14]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[15]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[16]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[17]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[18]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[19]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[20]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[21]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[22]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[23]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[24]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[25]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[26]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[27]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[28]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[29]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[30]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[31]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[32]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_0[33]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[0]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[1]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[2]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[3]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[4]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[5]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[6]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[7]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[8]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[9]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[10]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[11]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[12]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[13]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[14]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[15]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[16]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[17]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[18]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[19]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[20]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[21]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[22]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[23]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[24]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[25]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[26]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[27]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[28]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[29]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[30]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[31]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[32]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO_1[33]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[10]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[11]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[12]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[13]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[14]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRAM_DQ[15]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------------+
; Input Transition Times                                                 ;
+---------------------+--------------+-----------------+-----------------+
; Pin                 ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+--------------+-----------------+-----------------+
; GPIO_2_IN[0]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2_IN[1]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2_IN[2]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0_IN[0]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0_IN[1]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1_IN[0]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1_IN[1]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[0]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[1]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[2]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[3]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[4]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[5]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[6]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[7]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[8]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[9]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[10]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[11]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_2[12]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[0]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[1]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[2]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[3]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[4]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[5]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[6]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[7]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[8]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[9]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[10]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[11]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[12]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[13]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[14]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[15]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[16]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[17]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[18]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[19]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[20]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[21]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[22]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[23]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[24]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[25]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[26]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[27]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[28]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[29]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[30]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[31]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[32]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_0[33]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[0]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[1]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[2]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[3]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[4]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[5]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[6]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[7]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[8]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[9]           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[10]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[11]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[12]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[13]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[14]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[15]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[16]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[17]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[18]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[19]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[20]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[21]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[22]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[23]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[24]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[25]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[26]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[27]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[28]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[29]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[30]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[31]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[32]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO_1[33]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[0]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[1]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[2]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[3]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[4]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[5]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[6]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[7]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[8]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[9]          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[10]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[11]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[12]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[13]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[14]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DRAM_DQ[15]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_50            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; EPCS_DATA0          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; KEY[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; KEY[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; G_SENSOR_INT        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ADC_SDAT            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tms ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tck ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tdi ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; LED[0]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[1]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[2]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[3]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; LED[4]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; LED[5]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.09 V              ; -0.0119 V           ; 0.277 V                              ; 0.297 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.09 V             ; -0.0119 V          ; 0.277 V                             ; 0.297 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; LED[6]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; LED[7]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.09 V              ; -0.0119 V           ; 0.277 V                              ; 0.297 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.09 V             ; -0.0119 V          ; 0.277 V                             ; 0.297 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; DRAM_ADDR[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; DRAM_BA[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_BA[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_CAS_N          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_CKE            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_CLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_CS_N           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.09 V              ; -0.0123 V           ; 0.281 V                              ; 0.305 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.09 V             ; -0.0123 V          ; 0.281 V                             ; 0.305 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; DRAM_DQM[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQM[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_RAS_N          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_WE_N           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; EPCS_ASDO           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.51e-08 V                   ; 3.1 V               ; -0.0261 V           ; 0.227 V                              ; 0.278 V                              ; 1.5e-09 s                   ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.51e-08 V                  ; 3.1 V              ; -0.0261 V          ; 0.227 V                             ; 0.278 V                             ; 1.5e-09 s                  ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; EPCS_DCLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.05e-09 V                   ; 3.21 V              ; -0.181 V            ; 0.16 V                               ; 0.253 V                              ; 2.77e-10 s                  ; 2.32e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.05e-09 V                  ; 3.21 V             ; -0.181 V           ; 0.16 V                              ; 0.253 V                             ; 2.77e-10 s                 ; 2.32e-10 s                 ; No                        ; Yes                       ;
; EPCS_NCSO           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.51e-08 V                   ; 3.1 V               ; -0.0261 V           ; 0.227 V                              ; 0.278 V                              ; 1.5e-09 s                   ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.51e-08 V                  ; 3.1 V              ; -0.0261 V          ; 0.227 V                             ; 0.278 V                             ; 1.5e-09 s                  ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; G_SENSOR_CS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; ADC_CS_N            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; ADC_SADDR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; ADC_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_2[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_2[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_2[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_2[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_2[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_2[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_2[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_2[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.09 V              ; -0.0119 V           ; 0.277 V                              ; 0.297 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.09 V             ; -0.0119 V          ; 0.277 V                             ; 0.297 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; GPIO_2[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_2[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_0[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[13]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[14]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[15]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.09 V              ; -0.0123 V           ; 0.281 V                              ; 0.305 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.09 V             ; -0.0123 V          ; 0.281 V                             ; 0.305 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; GPIO_0[16]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[17]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[18]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[19]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[20]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[21]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[22]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[23]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[24]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[25]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[26]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[27]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[28]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.09 V              ; -0.0123 V           ; 0.281 V                              ; 0.305 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.09 V             ; -0.0123 V          ; 0.281 V                             ; 0.305 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; GPIO_0[29]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[30]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[31]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[32]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_0[33]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.09 V              ; -0.0123 V           ; 0.281 V                              ; 0.305 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.09 V             ; -0.0123 V          ; 0.281 V                             ; 0.305 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; GPIO_1[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[13]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[14]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[15]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[16]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[17]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[18]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[19]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[20]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[21]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[22]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[23]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[24]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[25]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[26]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.09 V              ; -0.0119 V           ; 0.277 V                              ; 0.297 V                              ; 4.54e-09 s                  ; 3.32e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.09 V             ; -0.0119 V          ; 0.277 V                             ; 0.297 V                             ; 4.54e-09 s                 ; 3.32e-09 s                 ; No                        ; No                        ;
; GPIO_1[27]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[28]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; GPIO_1[29]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[30]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[31]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[32]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; GPIO_1[33]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.16 V              ; -0.11 V             ; 0.302 V                              ; 0.22 V                               ; 4.82e-10 s                  ; 4.27e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.16 V             ; -0.11 V            ; 0.302 V                             ; 0.22 V                              ; 4.82e-10 s                 ; 4.27e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[10]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[11]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[12]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[13]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[14]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.24e-08 V                   ; 3.14 V              ; -0.115 V            ; 0.31 V                               ; 0.241 V                              ; 5.06e-10 s                  ; 4.37e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.24e-08 V                  ; 3.14 V             ; -0.115 V           ; 0.31 V                              ; 0.241 V                             ; 5.06e-10 s                 ; 4.37e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[15]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.54e-08 V                   ; 3.14 V              ; -0.074 V            ; 0.343 V                              ; 0.194 V                              ; 7.35e-10 s                  ; 6.36e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 1.54e-08 V                  ; 3.14 V             ; -0.074 V           ; 0.343 V                             ; 0.194 V                             ; 7.35e-10 s                 ; 6.36e-10 s                 ; No                        ; No                        ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.07e-08 V                   ; 3.12 V              ; -0.0141 V           ; 0.213 V                              ; 0.204 V                              ; 6.63e-10 s                  ; 1.57e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 6.07e-08 V                  ; 3.12 V             ; -0.0141 V          ; 0.213 V                             ; 0.204 V                             ; 6.63e-10 s                 ; 1.57e-09 s                 ; Yes                       ; No                        ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; LED[0]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[1]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[2]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[3]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; LED[4]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; LED[5]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.08 V              ; -0.00666 V          ; 0.298 V                              ; 0.277 V                              ; 5.29e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.08 V             ; -0.00666 V         ; 0.298 V                             ; 0.277 V                             ; 5.29e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; LED[6]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; LED[7]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.08 V              ; -0.00666 V          ; 0.298 V                              ; 0.277 V                              ; 5.29e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.08 V             ; -0.00666 V         ; 0.298 V                             ; 0.277 V                             ; 5.29e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; DRAM_ADDR[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; DRAM_ADDR[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_ADDR[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; DRAM_BA[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_BA[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_CAS_N          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_CKE            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_CLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_CS_N           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.08 V              ; -0.00675 V          ; 0.232 V                              ; 0.283 V                              ; 5.31e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.08 V             ; -0.00675 V         ; 0.232 V                             ; 0.283 V                             ; 5.31e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; DRAM_DQM[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQM[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_RAS_N          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_WE_N           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; EPCS_ASDO           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 4.54e-06 V                   ; 3.09 V              ; -0.0134 V           ; 0.121 V                              ; 0.243 V                              ; 1.77e-09 s                  ; 1.7e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 4.54e-06 V                  ; 3.09 V             ; -0.0134 V          ; 0.121 V                             ; 0.243 V                             ; 1.77e-09 s                 ; 1.7e-09 s                  ; Yes                       ; Yes                       ;
; EPCS_DCLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.123 V            ; 0.134 V                              ; 0.323 V                              ; 3.02e-10 s                  ; 2.85e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.123 V           ; 0.134 V                             ; 0.323 V                             ; 3.02e-10 s                 ; 2.85e-10 s                 ; Yes                       ; No                        ;
; EPCS_NCSO           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 4.54e-06 V                   ; 3.09 V              ; -0.0134 V           ; 0.121 V                              ; 0.243 V                              ; 1.77e-09 s                  ; 1.7e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 4.54e-06 V                  ; 3.09 V             ; -0.0134 V          ; 0.121 V                             ; 0.243 V                             ; 1.77e-09 s                 ; 1.7e-09 s                  ; Yes                       ; Yes                       ;
; G_SENSOR_CS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; ADC_CS_N            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; ADC_SADDR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; ADC_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; GPIO_2[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; GPIO_2[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; GPIO_2[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.08 V              ; -0.00666 V          ; 0.298 V                              ; 0.277 V                              ; 5.29e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.08 V             ; -0.00666 V         ; 0.298 V                             ; 0.277 V                             ; 5.29e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; GPIO_2[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_2[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[13]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[14]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[15]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.08 V              ; -0.00675 V          ; 0.232 V                              ; 0.283 V                              ; 5.31e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.08 V             ; -0.00675 V         ; 0.232 V                             ; 0.283 V                             ; 5.31e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; GPIO_0[16]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[17]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[18]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[19]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[20]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[21]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[22]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[23]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[24]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[25]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[26]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[27]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[28]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.08 V              ; -0.00675 V          ; 0.232 V                              ; 0.283 V                              ; 5.31e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.08 V             ; -0.00675 V         ; 0.232 V                             ; 0.283 V                             ; 5.31e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; GPIO_0[29]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[30]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[31]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[32]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_0[33]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; GPIO_1[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.08 V              ; -0.00675 V          ; 0.232 V                              ; 0.283 V                              ; 5.31e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.08 V             ; -0.00675 V         ; 0.232 V                             ; 0.283 V                             ; 5.31e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; GPIO_1[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[13]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[14]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[15]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[16]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[17]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[18]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[19]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[20]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; GPIO_1[21]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[22]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[23]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[24]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[25]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[26]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.08 V              ; -0.00666 V          ; 0.298 V                              ; 0.277 V                              ; 5.29e-09 s                  ; 4.2e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.08 V             ; -0.00666 V         ; 0.298 V                             ; 0.277 V                             ; 5.29e-09 s                 ; 4.2e-09 s                  ; Yes                       ; No                        ;
; GPIO_1[27]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; GPIO_1[28]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[29]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[30]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[31]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[32]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; GPIO_1[33]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.13 V              ; -0.0781 V           ; 0.202 V                              ; 0.359 V                              ; 6.54e-10 s                  ; 5e-10 s                     ; No                         ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.13 V             ; -0.0781 V          ; 0.202 V                             ; 0.359 V                             ; 6.54e-10 s                 ; 5e-10 s                    ; No                        ; No                        ;
; DRAM_DQ[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[10]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[11]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[12]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[13]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[14]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.99e-06 V                   ; 3.11 V              ; -0.0717 V           ; 0.209 V                              ; 0.168 V                              ; 6.66e-10 s                  ; 6.19e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.99e-06 V                  ; 3.11 V             ; -0.0717 V          ; 0.209 V                             ; 0.168 V                             ; 6.66e-10 s                 ; 6.19e-10 s                 ; Yes                       ; No                        ;
; DRAM_DQ[15]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2e-06 V                      ; 3.12 V              ; -0.0547 V           ; 0.276 V                              ; 0.181 V                              ; 9.17e-10 s                  ; 8.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2e-06 V                     ; 3.12 V             ; -0.0547 V          ; 0.276 V                             ; 0.181 V                             ; 9.17e-10 s                 ; 8.31e-10 s                 ; Yes                       ; No                        ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.88e-06 V                   ; 3.1 V               ; -0.00497 V          ; 0.088 V                              ; 0.154 V                              ; 8.34e-10 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.88e-06 V                  ; 3.1 V              ; -0.00497 V         ; 0.088 V                             ; 0.154 V                             ; 8.34e-10 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; LED[0]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[1]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[2]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[3]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; LED[4]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; LED[5]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.48 V              ; -0.0162 V           ; 0.354 V                              ; 0.317 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.48 V             ; -0.0162 V          ; 0.354 V                             ; 0.317 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; LED[6]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; LED[7]              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.48 V              ; -0.0162 V           ; 0.354 V                              ; 0.317 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.48 V             ; -0.0162 V          ; 0.354 V                             ; 0.317 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; DRAM_ADDR[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_ADDR[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_ADDR[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; DRAM_BA[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_BA[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_CAS_N          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_CKE            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_CLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_CS_N           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.48 V              ; -0.0173 V           ; 0.356 V                              ; 0.324 V                              ; 3.89e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.48 V             ; -0.0173 V          ; 0.356 V                             ; 0.324 V                             ; 3.89e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; DRAM_DQM[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQM[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_RAS_N          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_WE_N           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; EPCS_ASDO           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.83e-07 V                   ; 3.49 V              ; -0.0372 V           ; 0.265 V                              ; 0.238 V                              ; 1.3e-09 s                   ; 1.28e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.83e-07 V                  ; 3.49 V             ; -0.0372 V          ; 0.265 V                             ; 0.238 V                             ; 1.3e-09 s                  ; 1.28e-09 s                 ; No                        ; No                        ;
; EPCS_DCLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.54e-08 V                   ; 3.66 V              ; -0.26 V             ; 0.41 V                               ; 0.32 V                               ; 1.57e-10 s                  ; 2.15e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.54e-08 V                  ; 3.66 V             ; -0.26 V            ; 0.41 V                              ; 0.32 V                              ; 1.57e-10 s                 ; 2.15e-10 s                 ; No                        ; Yes                       ;
; EPCS_NCSO           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.83e-07 V                   ; 3.49 V              ; -0.0372 V           ; 0.265 V                              ; 0.238 V                              ; 1.3e-09 s                   ; 1.28e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.83e-07 V                  ; 3.49 V             ; -0.0372 V          ; 0.265 V                             ; 0.238 V                             ; 1.3e-09 s                  ; 1.28e-09 s                 ; No                        ; No                        ;
; G_SENSOR_CS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; ADC_CS_N            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; ADC_SADDR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; ADC_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_2[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_2[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; GPIO_2[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_2[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_2[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_2[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; GPIO_2[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; GPIO_2[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_2[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_2[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_2[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.48 V              ; -0.0162 V           ; 0.354 V                              ; 0.317 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.48 V             ; -0.0162 V          ; 0.354 V                             ; 0.317 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; GPIO_2[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_2[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_0[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[13]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[14]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[15]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.48 V              ; -0.0173 V           ; 0.356 V                              ; 0.324 V                              ; 3.89e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.48 V             ; -0.0173 V          ; 0.356 V                             ; 0.324 V                             ; 3.89e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; GPIO_0[16]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[17]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[18]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[19]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[20]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[21]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[22]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[23]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[24]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[25]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[26]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[27]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[28]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.48 V              ; -0.0173 V           ; 0.356 V                              ; 0.324 V                              ; 3.89e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.48 V             ; -0.0173 V          ; 0.356 V                             ; 0.324 V                             ; 3.89e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; GPIO_0[29]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[30]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[31]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[32]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_0[33]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[0]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; GPIO_1[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[8]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[9]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[10]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.48 V              ; -0.0173 V           ; 0.356 V                              ; 0.324 V                              ; 3.89e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.48 V             ; -0.0173 V          ; 0.356 V                             ; 0.324 V                             ; 3.89e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; GPIO_1[11]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[12]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[13]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[14]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[15]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[16]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[17]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[18]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[19]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[20]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; GPIO_1[21]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[22]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[23]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[24]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[25]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[26]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.48 V              ; -0.0162 V           ; 0.354 V                              ; 0.317 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.48 V             ; -0.0162 V          ; 0.354 V                             ; 0.317 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; GPIO_1[27]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; GPIO_1[28]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO_1[29]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[30]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[31]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[32]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; GPIO_1[33]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.6 V               ; -0.127 V            ; 0.302 V                              ; 0.21 V                               ; 4.55e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.6 V              ; -0.127 V           ; 0.302 V                             ; 0.21 V                              ; 4.55e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRAM_DQ[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[10]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[11]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[12]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[13]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[14]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; DRAM_DQ[15]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; altera_reserved_tdo ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 4.9e-07 V                    ; 3.52 V              ; -0.0234 V           ; 0.372 V                              ; 0.263 V                              ; 5.16e-10 s                  ; 1.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 4.9e-07 V                   ; 3.52 V             ; -0.0234 V          ; 0.372 V                             ; 0.263 V                             ; 5.16e-10 s                 ; 1.44e-09 s                 ; No                        ; No                        ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                         ;
+----------------------------------------------------+----------------------------------------------------+------------+------------+----------+----------+
; From Clock                                         ; To Clock                                           ; RR Paths   ; FR Paths   ; RF Paths ; FF Paths ;
+----------------------------------------------------+----------------------------------------------------+------------+------------+----------+----------+
; altera_reserved_tck                                ; altera_reserved_tck                                ; 1724       ; 0          ; 32       ; 2        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; altera_reserved_tck                                ; false path ; 0          ; 0        ; 0        ;
; CLOCK_50                                           ; CLOCK_50                                           ; 12766      ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; CLOCK_50                                           ; 22         ; 0          ; 0        ; 0        ;
; altera_reserved_tck                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; false path ; false path ; 0        ; 0        ;
; CLOCK_50                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 19         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 367067     ; 64         ; 224      ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 27         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 17         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 11         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 13571      ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 10         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 730        ; 5          ; 15       ; 0        ;
+----------------------------------------------------+----------------------------------------------------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                          ;
+----------------------------------------------------+----------------------------------------------------+------------+------------+----------+----------+
; From Clock                                         ; To Clock                                           ; RR Paths   ; FR Paths   ; RF Paths ; FF Paths ;
+----------------------------------------------------+----------------------------------------------------+------------+------------+----------+----------+
; altera_reserved_tck                                ; altera_reserved_tck                                ; 1724       ; 0          ; 32       ; 2        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; altera_reserved_tck                                ; false path ; 0          ; 0        ; 0        ;
; CLOCK_50                                           ; CLOCK_50                                           ; 12766      ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; CLOCK_50                                           ; 22         ; 0          ; 0        ; 0        ;
; altera_reserved_tck                                ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; false path ; false path ; 0        ; 0        ;
; CLOCK_50                                           ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 19         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 367067     ; 64         ; 224      ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 27         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 17         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 11         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 13571      ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 10         ; 0          ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 730        ; 5          ; 15       ; 0        ;
+----------------------------------------------------+----------------------------------------------------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                  ;
+----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+
; From Clock                                         ; To Clock                                           ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+
; altera_reserved_tck                                ; altera_reserved_tck                                ; 81       ; 0        ; 3        ; 0        ;
; CLOCK_50                                           ; CLOCK_50                                           ; 437      ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; CLOCK_50                                           ; 3        ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 2611     ; 0        ; 32       ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 3        ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 368      ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 3        ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 104      ; 0        ; 1        ; 0        ;
+----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                   ;
+----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+
; From Clock                                         ; To Clock                                           ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+
; altera_reserved_tck                                ; altera_reserved_tck                                ; 81       ; 0        ; 3        ; 0        ;
; CLOCK_50                                           ; CLOCK_50                                           ; 437      ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; CLOCK_50                                           ; 3        ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; 2611     ; 0        ; 32       ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 3        ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] ; 368      ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 3        ; 0        ; 0        ; 0        ;
; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] ; 104      ; 0        ; 1        ; 0        ;
+----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 3     ; 3    ;
; Unconstrained Input Ports       ; 28    ; 28   ;
; Unconstrained Input Port Paths  ; 118   ; 118  ;
; Unconstrained Output Ports      ; 56    ; 56   ;
; Unconstrained Output Port Paths ; 91    ; 91   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Sep 25 10:23:14 2013
Info: Command: quartus_sta DE0_Nano -c DE0_Nano
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity alt_jtag_atlantic
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] 
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] 
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
        Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] 
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
        Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
    Info (332165): Entity altera_avalon_st_clock_crosser
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
    Info (332165): Entity altera_std_synchronizer
        Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info (332165): Entity dcfifo_v2j1
        Info (332166): set_false_path -from *write_delay_cycle* -to *dffpipe_rs_dgwp|dffpipe_nd9:dffpipe8|dffe9a* 
    Info (332165): Entity sld_jtag_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'DE0_Nano_SOPC/synthesis/submodules/altera_reset_controller.sdc'
Info (332104): Reading SDC File: 'DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_cpu.sdc'
Info (332104): Reading SDC File: 'DE0_Nano.SDC'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]} {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0]}
    Info (332110): create_generated_clock -source {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0]} -multiply_by 2 -phase -60.00 -duty_cycle 50.00 -name {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1]} {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[1]}
    Info (332110): create_generated_clock -source {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0]} -divide_by 5 -duty_cycle 50.00 -name {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]} {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2]}
    Info (332110): create_generated_clock -source {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|inclk[0]} -divide_by 25 -duty_cycle 50.00 -name {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]} {DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02 was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|spi_clk was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 1.695
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.695         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     9.964         0.000 CLOCK_50 
    Info (332119):    47.209         0.000 altera_reserved_tck 
    Info (332119):    87.442         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   247.819         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332146): Worst-case hold slack is 0.233
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.233         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     0.342         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
    Info (332119):     0.356         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):     0.357         0.000 CLOCK_50 
    Info (332119):     0.358         0.000 altera_reserved_tck 
Info (332146): Worst-case recovery slack is 2.275
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.275         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):    15.840         0.000 CLOCK_50 
    Info (332119):    48.469         0.000 altera_reserved_tck 
    Info (332119):    96.973         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   248.245         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332146): Worst-case removal slack is 0.885
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.885         0.000 altera_reserved_tck 
    Info (332119):     0.912         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
    Info (332119):     1.815         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     1.838         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):     2.840         0.000 CLOCK_50 
Info (332146): Worst-case minimum pulse width slack is 4.695
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.695         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     9.489         0.000 CLOCK_50 
    Info (332119):    49.537         0.000 altera_reserved_tck 
    Info (332119):    49.740         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   249.746         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332114): Report Metastability: Found 64 synchronizer chains.
    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.

    Info (332114): Number of Synchronizer Chains Found: 64
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
    Info (332114): Worst Case Available Settling Time: 14.700 ns
    Info (332114): 
    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02 was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|spi_clk was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 2.523
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.523         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):    10.948         0.000 CLOCK_50 
    Info (332119):    47.558         0.000 altera_reserved_tck 
    Info (332119):    88.724         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   248.036         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332146): Worst-case hold slack is 0.232
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.232         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     0.299         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
    Info (332119):     0.311         0.000 CLOCK_50 
    Info (332119):     0.311         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):     0.311         0.000 altera_reserved_tck 
Info (332146): Worst-case recovery slack is 2.577
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.577         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):    16.331         0.000 CLOCK_50 
    Info (332119):    48.703         0.000 altera_reserved_tck 
    Info (332119):    97.319         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   248.437         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332146): Worst-case removal slack is 0.791
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.791         0.000 altera_reserved_tck 
    Info (332119):     0.822         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
    Info (332119):     1.610         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     1.634         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):     2.558         0.000 CLOCK_50 
Info (332146): Worst-case minimum pulse width slack is 4.720
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.720         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     9.490         0.000 CLOCK_50 
    Info (332119):    49.495         0.000 altera_reserved_tck 
    Info (332119):    49.738         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   249.743         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332114): Report Metastability: Found 64 synchronizer chains.
    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.

    Info (332114): Number of Synchronizer Chains Found: 64
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
    Info (332114): Worst Case Available Settling Time: 15.302 ns
    Info (332114): 
    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|Start was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_ADC_READ:adc_spi_read|ADC_READ:ADC_READ_Inst|st.st_02 was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DE0_Nano_SOPC:DE0_Nano_SOPC_inst|TERASIC_SPI_3WIRE:gsensor_spi|SPI_3WIRE:SPI_3WIRE_inst|spi_clk was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 3.515
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.515         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):    14.343         0.000 CLOCK_50 
    Info (332119):    48.712         0.000 altera_reserved_tck 
    Info (332119):    92.677         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   248.755         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332146): Worst-case hold slack is 0.106
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.106         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     0.179         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
    Info (332119):     0.185         0.000 CLOCK_50 
    Info (332119):     0.186         0.000 altera_reserved_tck 
    Info (332119):     0.187         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
Info (332146): Worst-case recovery slack is 3.403
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.403         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):    17.509         0.000 CLOCK_50 
    Info (332119):    49.433         0.000 altera_reserved_tck 
    Info (332119):    98.210         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   248.993         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332146): Worst-case removal slack is 0.495
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.495         0.000 altera_reserved_tck 
    Info (332119):     0.500         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
    Info (332119):     1.070         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     1.079         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):     1.646         0.000 CLOCK_50 
Info (332146): Worst-case minimum pulse width slack is 4.749
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.749         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[0] 
    Info (332119):     9.209         0.000 CLOCK_50 
    Info (332119):    49.315         0.000 altera_reserved_tck 
    Info (332119):    49.751         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[2] 
    Info (332119):   249.776         0.000 DE0_Nano_SOPC_inst|altpll_sys_inst|sd1|pll7|clk[4] 
Info (332114): Report Metastability: Found 64 synchronizer chains.
    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.

    Info (332114): Number of Synchronizer Chains Found: 64
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
    Info (332114): Worst Case Available Settling Time: 17.013 ns
    Info (332114): 
    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 632 megabytes
    Info: Processing ended: Wed Sep 25 10:23:22 2013
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:09


