BEGIN:VCALENDAR
VERSION:2.0
CALSCALE:GREGORIAN
PRODID:UW-Madison-Physics-Events
BEGIN:VEVENT
SEQUENCE:0
UID:UW-Physics-Event-2309
DTSTART:20120301T160000Z
DURATION:PT1H0M0S
DTSTAMP:20260306T091711Z
LAST-MODIFIED:20120227T165312Z
LOCATION:5310 Chamberlin
SUMMARY:Challenges in Quantum Computer Architecture\, R. G. Herb Conde
 nsed Matter Seminar\, Ken Brown\, Schools of Chemistry & Biochemistry\
 ; Computational Science & Engineering\; and Physics\, Georgia Institut
 e of Technology
DESCRIPTION:The development of a large-scale quantum computer faces tw
 o challenges: faulty hardware components and the inability to copy qua
 ntum information. Despite the no-cloning theorem\, it is possible to u
 se fault-tolerant quantum error correction techniques to generate arbi
 trarily reliable logical components. In the context of an algorithm\, 
 the inability to copy quantum information requires that a block of dat
 a that needs to interact with two other data blocks must be transporte
 d first from one block and then to the other. Although it is widely ap
 preciated that the bulk of resources in a scalable quantum computers w
 ill be devoted to error correction\, the significant cost of communica
 tion during the computation is only now being understood [1]. This can
  have a dramatic effect on the utility of a quantum computer as a simu
 lator of other quantum systems [2].<br>
\n<br>
\nI will discuss method
 s for estimating the communication cost on two distinct hardware layou
 ts for ion trap quantum computation in the context of concatenated err
 or correcting codes. In the first hardware layout\, the ions are held 
 in multiple zones and communications is performed by physically shuttl
 ing ions between zones [3]. The second hardware layout uses photons to
  create entangled ions in distant traps by the process of heralded ent
 anglement [4]. These entangled ions are then used as teleportation cha
 nnels to transfer information. I will compare possible architectures f
 or arranging these systems on the logical level. Finally\, I will brie
 fly describe how these same architectural ideas can be applied in the 
 setting of topological error correction.<br>
\n<br>
\n[1] M.G. Whitney
 \, N. Isailovic\, Y. Patel and J. Kubiatowicz\, A fault tolerant\, are
 a efficient architecture for Shor's factoring algorithm\, Proc. of the
  39th Annual Intl. Symp. on Computer Architecture ( ISCA)\, 383 (2009)
 .<br>
\n<br>
\n[2]C. R. Clark\, T. S. Metodi\, S. D. Gasster\, and K. 
 R. Brown\, Resource requirements for fault-tolerant quantum simulation
 : the transverse Ising model ground state\, Phys. Rev. A 79\, 062314 (
 2009).<br>
\n<br>
\n[3] D. Kielpinski\, C. Monroe & D. J. Wineland\, A
 rchitecture for a large-scale ion-trap quantum computer\, Nature 417\,
  709 (2002).<br>
\n<br>
\n[4] L.-M. Duan and C. Monroe\, Quantum netwo
 rks with trapped ions \,Rev. Mod. Phys. 82\, 1209 (2010).<br>
\n<br>
\
 n<br>
\n
\n
URL:https://www.physics.wisc.edu/events/?id=2309
END:VEVENT
END:VCALENDAR